Technical Paper Home

Design & Verification

• Electrical Properties of ML and BL MoS2 GAA NS FETs With Source/Drain Metal Contacts (NYCU)

  Published on May 31, 2025

• A Lightweight Scan Instrumentation For Enhancing The Post-Silicon Test Efficiency in ICs (U. of Florida)

  Published on May 31, 2025

• Role of Josephson Junctions In Propelling Quantum Technologies Forward (LBNL, UC Berkeley, et al.)

  Published on May 31, 2025

• Optimization Approach For The Dispensing of Thermal Interface Material (KIT, Robert Bosch)

  Published on May 21, 2025

• Open-Source And Royalty-Free Confidential Computing For Embedded RISC-V Systems (IBM, Max Planck)

  Published on May 20, 2025

• Energy-Aware DL: The Interplay Between NN Efficiency And Hardware Constraints (Imperial College London, Cambridge)

  Published on May 20, 2025

• Customizing A LLM Model For VHDL Design of High-Performance MPUs (IBM)

  Published on May 18, 2025

• Floorplanning Method For Reducing Thermally-Induced Structural Stress In Chiplet Packages (Penn State, Intel, ASU et al.)

  Published on May 14, 2025

• Effects Of Hardware Prefetchers For Scientific Application Kernels Running on High-End Processors

  Published on May 14, 2025

• CFETs: Reliability of Complementary Field-Effect Transistors (TU Munich, IIT)

  Published on May 14, 2025
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