Special report on the return of the heterogeneous SoC; AI-created models; AI's impact on protocols; 1 MW AI server racks; 3D-IC verification; DDR5 requirements; edge-native AI; CPO for AI compute clusters.
AI's growing role in defect inspection and review; A/MS test coverage challenges; CPO test faces steep ramp; edge defect detection and classification; supply chain partnerships; verifiable AI for yield; I/O-limited testing; HBM reliability; WBG metrology.
Challenges for data centers in space; keeping security algorithms current becomes harder; pressure grows for Auto Ethernet in AIDVs; DFT in automotive; terabit Ethernet; hacking Xbox One; stress testing; home security.
Agentic verification; chiplet I/O vs. compute tradeoffs; on-die observability; using AI to monitor dashboards in chips; confusion grows with more interconnect options and tradeoffs; confusion over data movement standards; overcoming AI data movement bottlenecks; NoC verification; automating DRC in PCBs; scaling library characterization; interconnect workloads; physics reasoning.
Special report on TSV complexity leading to a manufacturing bottleneck; chiplet economics; solder now a critical factor for chip reliability; mask technology challenges; gap between lab performance and fab reality is growing wider as packages grow more complex; TSMC's new technology roadmap; atomistic modeling; dummy fill shines; better multi-die roadmaps; energy-aware AI HW.
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