Top Stories

I/O Design Challenges Grow In AI Data Centers And HPC Clusters
Physical I/Os can be a chokepoint for high-performance chips and high-speed interconnect protocols, requiring design tradeoffs and extra reliability measures.

Verification Methodologies Struggle To Keep Up With AI
Engineers are flooded with new capabilities. The problem now is how best to deploy them.

Executive Outlook: Agentic AI’s Impact On Chip Design
Can engineers trust AI to get everything right in semiconductor design and verification?

Designing Chips That Can Explain Themselves
On-die monitors, localized analytics, and lifecycle data are giving architects new ways to close the gap between design intent and silicon behavior.

Videos

How Far Left Can You Shift?
Complex chips require much more work earlier in the flow.

Signoff Of Synthesis-Optimized Registers
When is a complex chip design ready to be shipped to manufacturing?

Building Multi-Agent Systems For ASIC Flows
How agents can be used to divide and conquer IC design problems.

Opinion

Disturbance In Verification

We have started to see what may be the largest disturbance in the role of a verification engineer since the founding of the industry. Should you be worried?

Sponsor Blogs

Synopsys’ Frank Schirrmeister questions when verification should begin if it’s never fully complete, in How Far Left Can We Really Shift Verification?

Siemens EDA’s Keith Felton explains why system-centric co-design is essential for heterogeneous, in Realizing The Future Of 3D-IC Design.

Arteris’ André Bonnardot discusses how last-level cache helps manage data movement and reduces pressure on external memory subsystems, in Reducing Avoidable Memory Trips In HBM Systems.

Baya Systems’ Nandan Nayampally outlines what’s needed to keep data movement in sync with processors, in Wafer-Scale vs. Chiplets: The New War? Part 2.

Cadence’s Antti Lautanen finds tokens-per-watt is now the primary metric driving AI data center optimization, in More Massive Still: Why AI Infrastructure Demands A Unified Design Approach.

ChipAgents’ Tanay Biradar, Surya Gunukula, Tengxiao Liu, and Kexun Zhang look at the critical limitations of existing models and how to overcome them, in Introducing An Agentic LLM For Chip Design.

Keysight’s Kwan Wee Lee explains how to avoid synchronization and concurrency issues that commonly appear in multi-DUT systems, in Scaling Production Test Without Scaling Complexity.

Sponsor White Papers

Continuous Physics Reasoning: Definition, Minimum Criteria, and the Role of Foundation Models for Physics
A general-purpose system that reasons natively over physical structure with deterministic, solver-grade, out-of-the-box generality at manufacturing resolution.

UCIe vs. BoW: Practical Insights For Choosing The Right Chiplet Standards
An application-oriented perspective on chiplet interconnect standards and their implications for next-gen system design.

Automate the Pain Away: HW/SW Interface Design Methodology
How a connected design methodology helps engineering teams accelerate development while maintaining consistency across the SoC lifecycle.

Optimizing Curvilinear OPC: Vector- Based Site and Anchor Decoupling
An advanced framework that independently and dynamically controls OPC fragmentation and optimization.

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