Designing heterogeneously integrated packages necessitates a system-centric co-design approach.
The integration of heterogeneous chiplet technology has fundamentally transformed semiconductor design, enabling the efficient creation of sophisticated system-in-packages by assembling pre-designed or third-party IP onto high-performance interposers and advanced packages. This approach offers significant advantages over traditional monolithic designs, including enhanced performance, improved power efficiency, greater scalability and flexibility, and reduced costs. However, existing design tools and workflows, developed primarily for single-die devices, are insufficient to fully harness the potential of chiplet technology. This necessitates a system-centric approach, from early planning to final sign-off, to unlock the full potential of 2.5D/3D-IC designs.
Fig. 1: 3D-IC design.
This article outlines a robust methodology, exemplified by solutions like the Siemens Innovator3D IC product family, that facilitates system-level technology co-optimization (STCO). This approach enables comprehensive optimization of power, performance, area, cost, and reliability across all components: silicon, interposers, semiconductor packages, and PCBs. The goal is to empower design engineers, reduce reliance on specialized experts, foster seamless data exchange across diverse teams, and maintain digital continuity. This methodology also provides early, predictive insights into downstream performance and process effects, utilizing continuous verification to minimize iterative design cycles.
Fig. 2: System-level technology co-optimization powers a shift-left design process.
The creation of a comprehensive 3D digital twin of the entire device assembly is the foundation of streamlining 3D-IC design. This begins with aggregating design IP to construct a full-system 3D model. The digital twin model drives the creation of interfaces and bump arrays for chiplets, bridges, interposers, and substrates through heterogeneous system planning, resulting in a single, authoritative source of system connectivity. This system-level netlist is crucial for subsequent design and sign-off activities, including system-level layout versus schematic, logical equivalency checking, multiphysics analysis, and detailed physical verification.
Aggregating and managing the vast array of design data for a 3D digital twin presents significant challenges. Manual data processing is error-prone and lacks repeatability, compounded by the sheer volume and variety of data formats. The industry is addressing this through new, standardized data formats for improved collaboration, sharing, and consumption, but despite these efforts, randomized design data remains prevalent. Incorporating this dynamic data is challenging as designs evolve and updates are frequent. As IC and package designers work concurrently, seamlessly integrating new IP versions without overwriting existing data is crucial. Accurate and efficient data import and robust revision control management are essential throughout the design lifecycle.
Let’s look at the steps to successfully automate and streamline this essential process.
Fig. 3: Creating the digital twin.
The initial phase involves aggregating and integrating diverse source design IP to construct a 3D digital twin model of the entire design assembly. The digital twin is used to explore and define an integration scenario that aligns with power, performance, area, and cost (PPA&C) targets. This prototyping, or pathfinding, process necessitates specialized EDA tools like Innovator3D IC Integrator.
Effective data management is paramount, especially when multiple chiplets are concurrently under development. Bi-directional exchanges of design changes must be meticulously tracked to ensure all design teams are aware of the latest data versions and their integration status. This work-in-progress data management is vital for determining which versions of netlists, spreadsheets, and Verilog files are incorporated into the final design before tape-out.
While many source design data formats are well-established, they often require significant skill for correct integration. Recent industry efforts, such as IEEE 3Dblox, OCP CDX, and JEDEC JEP30 Part Model, aim to develop higher-level, intelligent data formats to simplify initial design set up. These standards promote interoperability, standardize interface protocols for chiplet compatibility, and streamline the exchange of comprehensive component information, ultimately accelerating time-to-market.
Hierarchical design disaggregates large, complex designs into smaller, manageable building blocks. Many design structures exhibit repeatable patterns that can be represented as parameterized objects, a form of hierarchical design capture. Traditional package design solutions, modeling each device as a single, flat entity, are time-consuming, with ECOs often relying on static, unverified spreadsheets.
Representing devices as hierarchical building blocks allows designers to define topological pin regions with key pin attributes—including connectivity—using formulas, regular expressions, and design attribute tokens. Power distribution networks are typically implemented across various geometric regions with bump assignment schemes tailored to specific physical routing, such as checkerboard patterns.
An efficient method for representing these structures is as a set of parameterized pin regions. For instance, a silicon interposer design with four high-bandwidth memories (HBM) can be efficiently constructed using a die-to-die building block. Package designers leverage these interfaces and parameterized pin regions to define required pin patterns, numbering, and signal assignments.
After pins are generated for the core design, it can be exported as a part and imported into higher levels of hierarchy for system assembly, or as a library exchange format model for IC design implementation. Parameterized pin regions facilitate easy construction of die-to-die interface regions, such as HBM protocol signal sets. Hierarchical device planning in Innovator3D IC Integrator, combined with smart parametric pin-regions, enables rapid and efficient creation of complex package designs, with iterative updates performed in minutes or seconds.
Fig. 4: Silicon interposer soft IP SoC planning with parametrized pin regions: (a) prior to pin generation, (b) after the VDD and VSS pins are generated.
Rapid advancements in heterogeneous integration packaging, driven by AI and hyperscaling, are pushing substrate designers beyond existing methodologies. Designs with over 50 million total pins and hundreds of thousands of connections are becoming commonplace. Hybrid and direct bonding technologies promise millions of bump connections at densities of 25000 to 50000 per mm², rendering traditional spreadsheet-based approaches inadequate for managing complex hierarchical connectivity.
As each design component is introduced, it must be connected to other system components. Spreadsheet-based design requires defining every connection as a scalar, which is tedious and error-prone for high-width interfaces like HBM. Heterogeneous integration also introduces challenges with diverse connectivity source data formats.
To manage this explosion of die-to-die connections, substrate designers are adopting language-based design to define system connectivity. Writing Verilog RTL with proper bus notation is more efficient and less error-prone than bit-by-bit spreadsheet definitions or custom Excel macros, which cannot scale to millions of bumps.
Advanced heterogeneously integrated package and interposer designs is a system integration task. Designers synthesize input from various stakeholders, often working concurrently, into an electrically and physically correct functional design. Innovator3D IC Integrator manages this by constructing and maintaining the 3D digital twin model of the entire device. Its hierarchical device planning capabilities allow for defining and optimizing chiplet or ASIC floorplans and external interface assignments to meet PPA&C targets. Parameterized “smart” pin regions simplify bump plan creation, editing, and optimization.
Once connected, the system-level netlist requires functional verification. Traditional methods are labor-intensive, time-consuming, and often non-exhaustive or too late. Formal verification, automated and fast, exhaustively verifies all interconnections between dies/chiplets.
Designing silicon bridge dies and interposers into advanced semiconductor packages addresses the critical need for ultra-high-density, low-latency, and power-efficient communication between heterogeneous chiplets. These components act as sophisticated wiring layers, integrating diverse functionalities (CPUs, GPUs, HBM, accelerators) into a single, compact package. This architecture provides significantly higher bandwidth densities and shorter interconnect distances than traditional organic substrates, which is crucial for modern AI, hyperscaler, and high-performance computing applications.
The definition of bridges and interposers is driven by the connectivity of the devices they interconnect. The most efficient and reliable creation method is to derive them as a function of the devices they connect, leveraging an already existing and verified netlist, as accomplished by Innovator3D IC Integrator.
Innovator3D IC Integrator uniquely represents the entire system—dies, chiplets, bridges/interposers, packages, and PCBs—within a single, cockpit-driven environment. From early hierarchical device planning with parametric pin regions to final sign-off, it constructs a cohesive 3D digital twin model by consuming and controlling revisions of design IP data in various formats and levels of completeness. This ensures accurate component and layer relationships by accounting for placement, stacking, and bump/scale compensation.
With the 3D digital twin constructed, the design is ready for device placement and connectivity optimization, early thermal evaluation, route resource planning and feasibility, and power delivery network (PDN) prototyping.
Designing heterogeneously integrated semiconductor packages necessitates a system-centric co-design approach. Optimizing individual assembly levels in isolation risks compromising overall device effectiveness. Reintegrating diverse design elements into a prototype package assembly with sufficient fidelity for predictive multiphysics analysis. This analysis provides critical information, including connectivity evaluation, which is fed back to the silicon team to reconsider functional partitioning and IO pad rings.
Fig. 5: A fully floorplanned design in Innovator3D IC Integrator.
Engineering teams need a methodology that enables STCO for power, performance, area, cost, and reliability across silicon, interposers, package substrates, and system PCBs. With Siemens’ Innovator3D IC solution suite, design engineers are empowered, reducing their dependency on domain-centric experts and eliminating iterations with early insight into downstream performance and process effects. This methodology also provides scalability for managing heterogeneous data across enterprise-wide teams and maintaining digital continuity.
Once ASICs, chiplets, and memory are loaded, the focus shifts to device assembly placement and connectivity optimization—the core of STCO. Logic and memory devices (e.g., HBM stacks) require high-speed, high-bandwidth interfaces, necessitating close proximity, often achieved via silicon bridge devices connecting chiplet microbumps or hybrid-bond pads.
Most multi-device semiconductor packages also require substrate stiffeners, seal rings, thermal interface materials, and heat spreaders for thermal management, rigidity, and encapsulation. These mechanical objects attach to the package or interposer substrate and mount onto or across chiplets, impacting placement by occupying real estate and requiring clearance to prevent shorting.
During package pathfinding, designers must visualize and manipulate these components, editing them for integration and incorporating them into predictive analyses (e.g., thermal, mechanical stress). Early analysis assesses mechanical part performance, enabling timely corrective action.
Connectivity planning across substrate boundaries typically focuses on high-performance die-to-die interfaces (e.g., UCIe, HBM) and die-interposer-package or die-package-PCB connections. STCO aims to communicate optimized design intent to physical implementation tools, which typically view only one assembly level. STCO enables architectural and technology trade-offs for high-performance, cost-effective solutions in the shortest time, from physical planning and validation to detailed layout with in-process performance modeling. It facilitates solution-space exploration to balance resources across all domains.
Enabling STCO requires new levels of intelligence in design tools, leveraging machine learning and AI. For example, to optimize system-level logical netlist assignments between chiplets, Innovator3D IC Integrator uses unique machine learning algorithms to concurrently optimize connectivity and device pin and bump assignments across all hierarchy levels.
After optimization of connectivity, the next step is planning a PDN to provide sufficient and stable power, using metal-filled shapes or interdigitated stripes. Increased power and performance demands in semiconductor packages have escalated power delivery challenges, making “shift-left” power delivery analysis critical.
Integrating multiple dies into high-density heterogeneous packages amplifies complexity due to multiple rails and varied die current draws. Spatial constraints in dense designs challenge adequate voltage and current supply. Copper scarcity often necessitates additional package layers for diverse chiplet current requirements.
PDNs can coexist with signal routing, but this causes congestion, so they are typically on dedicated metal layers. After prototyping, the PDN is analyzed for suitability. Designers must predict behavior early and make trade-offs. Identifying significant DC-drop issues early is recommended, prioritizing problem detection over sign-off accuracy to prevent costly changes. The goal is to quickly identify major PDN flaws, not pinpoint accuracy.
Once DC-drop requirements are met, the focus shifts to metal density across each layer. Imbalances contribute to substrate warpage. Substrate vendors provide ideal density ratios; if a layer falls outside, additional metal areas are incorporated to balance layers in the overall design. Innovator3D IC Integrator achieves this balancing act with metal density calculation and automatic addition of user-defined metal areas.
Electronics must operate within strict temperature limits. However, complex thermal interactions in 2.5D and 3D-IC multi-die packages jeopardize device performance, behavior, and reliability. Temperatures, gradients, and swings directly influence electrical characteristics. Therefore, after floorplan optimization, thorough thermal performance evaluation is imperative to ensure co-design optimizations do not introduce unmanageable thermal challenges.
Fig. 6: Early predictive thermal analysis results during pathfinding using Innovator3D IC Integrator coupled with Calibre 3DThermal.
Vertical chiplet stacking in 3D-ICs impedes traditional heat escape. Thinning dies further compounds this by significantly increasing lateral thermal resistance. Early predictive thermal analysis during pathfinding is critical. Innovator3D IC Integrator and Calibre 3DThermal achieve this by modeling the entire device assembly for thermal issues. Delaying this until detailed implementation risks costly remedies or unsatisfactory performance.
After connectivity optimization, routing begins of the thousands of connections and interfaces found in multi-chiplet packages. Designers must identify related signal groups (interfaces, buses) and plan their path from chiplet bump fields to target bumps or package substrate C4 bumps. This involves managing multiple groups, considering routing real estate and channels, and ensuring electrical performance.
Traditional methods require manual or automatic routing without pre-planning, leading to bump field blockages, congestion, and channel blockages due to lack of a holistic view. This results in multiple rip-up and retry iterations, compromising route quality with excessive vias, increased length, and signal integrity issues (delay, impedance, reflections).
Combining bus signals into hierarchical connectivity bundles (data paths), supported by Innovator3D IC Integrator, allows higher-level route planning. This enables consideration of available substrate routing real estate to map desired paths for downstream detailed routing.
With a fully placed and floorplanned design, a DC-drop verified preliminary PDN, and critical interface/data bus connectivity planned, the design is ready for finalization, which we will cover in our next article in this four-part series on streamlining 3D-IC design that will appear here over the next few months.
To learn more on how to improve your 3D-IC flow, please check out the new series of eBooks from Siemens on Streamlining 3D-IC design:
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