PDN Challenges In DRAM-Based Compute-In-Memory Systems (UT Austin)


A new technical paper, "A comparative study on power delivery aspects of compute-in/near-memory approaches using DRAM," was published by researchers at UT Austin. Abstract "Compute-in-memory (PIM) mitigates the memory wall by performing computation within memory, reducing data movement and improving energy efficiency. DRAM-based PIM is particularly attractive due to its high density, matu... » read more

Power Integrity Without Blind Spots: A System Level Approach To 3D-ICs


Power delivery has become one of the defining challenges of next-generation semiconductor systems. As AI, high-performance computing, and data-centric workloads drive higher performance and tighter integration, traditional 2D SoC design approaches are reaching their limits. The industry’s shift toward 2.5D and 3D heterogeneous integration promises breakthroughs in performance and efficiency�... » read more

Detect, Diagnose, And Debug Using Sensors And Functional Monitoring


By Hari Mani, Henrique Mendes, and Robert Wilcox Modern AI workloads drive an extremely "spiky" power profile where current demands surge to hundreds of Amps within nanoseconds, clashing with the tighter operating ranges of advanced process nodes as they push below 0.8V. This creates a physical bottleneck: the on-die power delivery network (PDN) cannot sustain the instantaneous curren... » read more

Will 2026 Be Dominated By AI?


Many opportunities and problems became highly interlinked in 2025, fueled by the historic growth in everything AI. But how close are we coming to breaking points, and what are people doing to mitigate them? That is the story that will unfold this year. AI's penetration into an increasing number of workloads is placing almost quadratic demands on compute, memory, interconnect, and the archite... » read more

Robust Dynamic Voltage Droop Mitigation And Power Management


Power management is one of the keys for developing successful semiconductors products. There are virtually no applications for which power consumption is not a concern. Many creative solutions have been developed to reduce and manage power. Making these schemes work robustly in real-world conditions can be a challenge. This post considers widely used methods—voltage droop/glitch detection and... » read more

Setting Vmin With Transistor-Level PDN Telemetry


By Hans Yeager and Aakash Jani Curious about how to precisely determine the optimal voltage-regulator setpoints for your System-on-Chip (SoC)? In this video, we dive into how transistor-level Power Delivery Network (PDN) telemetry can revolutionize your approach to power, performance, and reliability. The voltage you set at the regulator (V-Min-VR) is rarely what the transistors actually ... » read more

Minimizing Voltage Loss And Improving Yield In Advanced GAA Chips


The problem: As metal pitch scaling shrinks to support the next generation of logic devices, the IR (or voltage) drop from conventional frontside connections has become a major challenge [1,2]. As electricity travels through a chip’s metal wiring, some voltage gets lost because wires have resistance. If the voltage drops too much, the chip’s transistors can’t get enough power and ... » read more

3D Stacked HBM and Accelerators for LLMs: Heat Management and PDN (Georgia Tech, SK Hynix)


A new technical paper titled "3D Stacked HBM and Compute Accelerators for LLM: Optimizing Thermal Management and Power Delivery Efficiency" was published by a researcher from Georgia Institute of Technology and SK Hynix. Abstract "Advanced packaging is becoming essential for designing hardware accelerators for large language models (LLMs). Different architectures such as 2.5D integration of... » read more

Frequency-Impedence Verification Of Power Delivery Network With HyperLynx PI For AMD Versal Adaptive SoC Devices


HyperLynx Decoupling analysis and the PDN Decoupling Optimizer are powerful tools for exploring various PDN structures and decoupling strategies. This paper presents a study showcasing the advantages of performing a HyperLynx decoupling analysis to verify PDN performance, and it highlights the extensive collaboration between Siemens and AMD in creating a complete system design flow for performi... » read more

SoC Power Delivery Network (PDN) Telemetry And Applications


PDN characterization needs visibility at the transistor. Through this white paper, we will learn why PDN visibility is crucial to each stage of the silicon lifecycle and its relation to power, performance, and in-field uptime. Register here to download the paper. » read more

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