Navigating the Metrology Maze For GAA FETs

Traditional measurement techniques are no longer sufficient. Here’s what comes next.


The chip industry is pushing the boundaries of innovation with the evolution of finFETs to gate-all-around (GAA) nanosheet transistors at the 3nm node and beyond, but it also is adding significant new metrology challenges.

GAA represents a significant advancement in transistor architecture, where the gate material fully encompasses the nanosheet channel. This approach allows for the vertical stacking of planar channels, leading to a notable increase in the effective channel width. By stacking these planar channels vertically, the effective channel width is increased, resulting in increased device drive current capability with less leakage, reduced power consumption, and enhanced performance.

This planar GAA structure also allows for modifiable channel widths, which both increases the complexity of transistor designs and the difficulty of achieving optimal power-performance tradeoffs. And because of the unique structure of GAA transistors, with their high-aspect ratio architecture and planar stacked nanosheets, it adds some new problems that still need to be solved.

As Philippe Leray, department director for advanced patterning at imec points out, a particular metrology need for GAA structures is “the ability to see through an optically opaque stack to measure buried dimensions and detect buried defects.”

The complex 3D architectures, high aspect-ratio structures, and the need for angstrom-level precision pose difficulties for traditional measurement techniques. In fact, each of those technologies has limitations today. And while recent advancements in established technologies coupled with new metrology innovations are starting to overcome those barriers, the solution may be a combination of different tools and methodologies, along with some new innovations.

Nanosheet formation metrology
The fabrication process of nanosheet structures involves multiple intricate steps, each with specific metrology needs. For example, during nanosheet formation on pre-patterned wafers, alternating layers of crystalline silicon (Si) and silicon-germanium (SiGe) sheets are epitaxially grown to thicknesses of approximately 8nm to 10nm each. Two of the critical measurements at this stage are the individual layer thicknesses and the germanium (Ge) concentrations in each SiGe sheet. Uniform thickness, material composition, and superlattice quality are all vital for control over channel dimensions and electrical characteristics of the device, and any variation can lead to poor device performance and significant yield loss.

Fig. 1: Epitaxial growth of Si and SiGe nanosheet lattice mismatch allows for etch selectivity. Source: Semiconductor Engineering/Gregory Haley.

Fig. 1: Epitaxial growth of Si and SiGe nanosheet lattice mismatch allows for etch selectivity. Source: Semiconductor Engineering/Gregory Haley. 

After patterning the nanosheets, it is important to measure the sheet-specific widths accurately. Scanning transmission electron microscopy (STEM) offers atomic-level resolution, allowing researchers to directly visualize individual atomic layers in the nanosheet structure, stacking order, defects, and crystal quality. STEM also can provide information about material composition by analyzing the contrast in the STEM images or using energy-dispersive X-ray spectroscopy (EDS) in combination with STEM.

But STEM isn’t perfect. Drawbacks include the requirement for specialized sample preparation, which can be time-consuming and may introduce artifacts during the process. STEM also is a destructive technique that necessitates the fabrication of ultra-thin samples, making it unsuitable for in-line, non-destructive measurements.

X-ray diffraction (HRXRD) has limitations, as well. It can accurately determine the composition and thickness of the nanosheets. By analyzing the X-ray diffraction patterns, researchers can infer the atomic arrangement and lattice strain, aiding in optimizing the nanosheet’s electronic properties. The primary challenge for HRXRD is acquisition time, which can take hours per wafer.

In-line Raman spectroscopy, meanwhile, offers fast and accurate measurement of the Ge composition for HVM. But sheet thickness measurements are difficult to obtain with this technique.

And scatterometry, also known as optical critical dimension (OCD) metrology — a non-destructive technique with the necessary speed for in-line HVM — uses a broadband light reflected off the surface of the nanosheet to provide information about Si channel thickness and the Ge content of the SiGe by measuring how the sample affects the characteristics of the reflected light as a function of wavelength.

Scatterometry may offer the most promising mix of measurements to satisfy HVM metrology needs for the epitaxial layers, however, the effectiveness of scatterometry in nanosheet metrology depends on factors such as the thickness of the layers, surface roughness, and accurate modeling.

Patterning and critical dimension metrology
Following epitaxial growth, photolithography and etching are used to define the pattern for the nanosheets that will form the channels of the GAA transistors. Polysilicon is then deposited and patterned to form a dummy gate, which helps protect the underlying channel region and align structures like the source and drain regions.

Line-edge roughness (LER), line-width roughness (LWR), and sidewall roughness (SWR) characterization are critical measurements at this stage of nanosheet patterning. These random variations can lead to unpredictable fluctuations in device performance, including variabilities in threshold voltages and current leakage. [1] 

CD-SEM measurements are commonly used to characterize the frequency domains and edge characteristics of LER and LWR. However, measuring LER and LWR in nanosheet patterning is challenging due to the complex three-dimensional nature of the structures. CD-SEMs are limited to top-down measurements that limit their ability to measure height, sidewall angles, and stacked nanosheets. Tilt CD-SEMs can obtain images from multiple angles by tilting either the sample or the electron gun to get a parallax view of the nanosheet structures, but this process slows measurement speeds and can introduce sample damage due to higher incidence of electron bombardment.

Selective etch metrology
After patterning, a highly-selective anisotropic etch step is used to carve away a portion of the SiGe layer, exposing the nanosheet sidewalls and laterally forming an indent between the layered sheets, which is then filled by the inner spacer via chemical vapor deposition (CVD) of a conformal layer of Si3N4 or SiO2.

The rate of SiGe etch is dependent on the concentration of Ge in the material, so measuring the Ge content throughout the process flow is important. Higher Ge content makes selective etching easier and faster to perform, with a higher likelihood of completely removing the SiGe material without damaging or eroding the silicon. But too much Ge can lead to challenges in material stability, facet formation, and strain management. It also may affect the electrical properties of the device, such as carrier mobility and threshold voltage. Therefore, careful measurements of the Ge content and etching parameters is essential.

“The more germanium you have, the better selectivity you have,” said Nick Keller, director of applications development at Onto Innovation. “But the more germanium you have, the more lattice strain you have, and if you have too much of a variation in a lattice between those two layers, then you can get different sorts of crystal graphic defects.”

Precise control over the width, thickness, and alignment of spacers is crucial, as small variations can significantly impact device performance. If an indent is too shallow, it may fail to isolate the channel and source/drain connections. If it is too deep, it will reduce the effective gate length and create a barrier for the gate channel. The inner spacer must completely fill the indent to ensure the gate length after channel release.

The metrology challenges include obtaining clear cross-sectional views for profile analysis, detecting small defects within complex geometries, measuring spacer thickness in narrow recesses, and performing non-destructive material composition and stress analyses.

The high aspect ratio structures of the GAA transistor are difficult to measure due to their depth and narrow width, particularly when it comes to determining the thickness of the nanosheets and the spaces between them. Traditional techniques struggle with these structures due to limitations in depth of focus or issues with shadowing, which can obscure parts of the structure and lead to inaccurate measurements.

According to Mary Breton, testsite layout and design manager at IBM Research, and colleagues, “The only existing in-line option to characterize the spacer width and coverage on device-like structures is a scatterometry-based model that is flexible enough to capture the possibilities for variation.” [2]

Fig. 2: Critical etching steps in the nanosheet transistor process flow include dummy gate etch (b), anisotropic pillar etch (c), isotropic inner spacer etch (e), and the channel release step (g). Source: N. Loubet, IBM

Fig. 2: Critical etching steps in the nanosheet transistor process flow include dummy gate etch (b), anisotropic pillar etch (c), isotropic inner spacer etch (e), and the channel release step (g). Source: N. Loubet, IBM

“High aspect ratios are not a problem for scatterometry,” says Keller. “In fact, it actually becomes better for scatterometry. When you increase your aspect ratio, you increase your effective optical thickness of these devices. With those structures, you get all these internal reflections, which are giving you more interactions and greater sensitivity.”

Source/Drain Epi
When the inner spacer process is complete, the source/drain (S/D) material is epitaxially grown where the nanosheet sidewalls are exposed between the gates. Proper nucleation requires connectivity with all the nanosheets in the stack, with the epi fully merged along the trench. The epi must stop above the top sheets on both sides of the trench without overfilling, or it could affect the follow-on process steps.

Ideal epi growth fills the trench, connects all three sheets, and stops above the top sheet. Non-ideal growth may overfill or underfill the trench, leading to downstream processing issues or connectivity problems. Epi nucleation and growth can be particularly challenging to measure, and any shifts in the epi process that alter growth rates or behavior must be captured in metrology solutions.

Techniques involving CD-SEM, scatterometry, machine learning, and AFM have been employed to characterize epi defects, localize them, measure epi height, and assess merge quality. Scatterometry, in particular, is useful for measuring epi height.

The primary metrology challenge for epi growth is identifying when all the nanosheet sheets are not fully connected, either through incomplete nucleation or growth. While height monitoring may detect connectivity issues with the top sheet, the bottom sheet’s connectivity might be hidden, resulting in a void at the bottom of the trench, which can’t be observed by these metrology techniques.

One potential solution for observing these undercuts and bottom sheet gaps is acoustic metrology that uses high-frequency sound waves to image structures that may be hidden from visual inspection.

“It depends on the material,” says Bill Zuckerman, product marketing manager at Nordson Test & Inspection. “Some materials absorb sound and are not a good application for acoustic measurements. But for other materials that are hardened, sound goes through them very well, and we get a lot more information from underfill materials. Sometimes we are able to see the density changes in those materials.”

Nearfield Instruments has taken a hybrid approach to acoustic metrology by using AFM to capture the vibrations reflected back by the sound waves. Their technique allows them to measure differing velocities of sound waves as they move through materials to determine their shape and potentially identify undercuts and hidden voids in epi growth.

“With different materials, the sound velocity is different orders, and your times of arrival are different,” says Hamed Sadeghian, CEO of Nearfield Instruments. “The amplitude and phase of the signal that comes to the surface can tell us how the underlying structures appear.”

Acoustic metrology can identify defects that are very small, down to two or three nanometers. But there is a tradeoff between material penetration and resolution. The higher the frequency of sound, the finer the resolution of the image. However, as the sound frequency increases, the penetration depth decreases. “It’s a tradeoff between frequency and resolution and penetration to achieve the best results that you can,” says Nordson’s Zuckerman.

Channel release etch
After the epi fill, the sacrificial SiGe layers and dummy gate are fully etched away during the channel release process, leaving silicon-based nanosheet layers that make up the channels. These are left suspended by the inner spacer and epi. This step requires critical measurements to both identify when SiGe is not completely removed, and also to determine if the suspended Si sheets sag due to mechanical instability or stiction.

The etch also might impact the sheet dimensions by removing too much Si in the process and impacting sheet thickness. Scatterometry is an effective measurement tool because it is sensitive to both the resulting geometry of the cavity and any remaining Ge. It is also important to monitor how the Si strain is impacted after removing the SiGe layer. Raman spectroscopy is a good solution here.

Replacement metal gate
When the etch is complete, a replacement metal gate is formed in these new voids by deposition of multiple thin-film materials, including high-k dielectric (HK) and metal films, within the cavities previously occupied by the SiGe sheets. This is the last step in GAA manufacturing, occurring just before the middle-of-line (MOL) and back-end processing stages.

These films are conformal to the silicon (Si) sheets and other exposed surfaces, with thicknesses on the order of angstroms to single nanometers. Such fine dimensions require highly sensitive and accurate measurements to characterize the top, bottom, and sidewall thicknesses of the films. If a given film is excessively thick, it may merge in the channel and prevent another film from wrapping around each sheet, compromising the device’s functionality.

Metrology solutions for the RMG process may include scatterometry for single-step measurements. However, a more robust solution can be achieved by combining scatterometry with techniques like X-ray photoelectron spectroscopy (XPS). Hybrid metrology utilizing XPS’ angstrom-level sensitivity and scatterometry’s geometric strengths has been shown to improve accuracy in characterizing conformal thin films over structures with varying aspect ratios. [3]

Fig. 3: Schematic of epi growth scenarios that need to be captured by in-line metrology. Source: Semiconductor Engineering/Gregory Haley

Fig. 3: Schematic of epi growth scenarios that need to be captured by in-line metrology. Source: Semiconductor Engineering/Gregory Haley

The complex three-dimensional structures of GAA nanosheet devices create unique challenges for metrology. Traditional measurement techniques struggle to accurately capture these intricate structures. Each nanosheet device consists of multiple layers of different materials, each with its own unique properties and measurement requirements. This complexity necessitates the use of multiple metrology techniques, each with its own strengths and weaknesses, to fully characterize the device.

Process variability adds another problem area. With so many variables in the fabrication process, from the deposition of the various layers to the etching of the nanosheets, there is a high degree of variability in the final device. This makes it crucial to have robust metrology solutions that work in concert to accurately measure and control this variability.

The development of hybrid metrology approaches, which combine data from multiple measurement techniques, appears to be a promising solution. By leveraging the strengths of each technique, these hybrid approaches can provide a more complete and accurate characterization of nanosheet devices.


  1. Haley, “Challenges Grow for CD-SEMs at 5nm and Beyond,” Semiconductor Engineering, April 11, 2023, Peters, “Strategies for Faster Ramps on 5nm Chips,” Semiconductor Engineering, April 12, 2022,
  2. Mary A. Breton, “Review of Nanosheet Metrology Opportunities for Technology Readiness,” J. Micro/Nanopatterning, Materials, and Metrology, Vol 21, Issue 2, 021206 (April 2022),
  3. A. Vaid et al., “Hybrid enabled thin film metrology using XPS and optical,” Proceedings Volume 9778, Metrology, Inspection, and Process Control for Microlithography XXX; 97780M (2016)

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