Challenges In Stacking, Shrinking And Inspecting Next-Gen Chips


Rick Gottscho, CTO of Lam Research, sat down with Semiconductor Engineering to discuss memory and equipment scaling, new market demands, and changes in manufacturing being driven by cost, new technologies, and the application of machine learning. What follows are excerpts of that conversation. SE: We have a lot of different memory technologies coming to market. What's the impact of that? ... » read more

An Inside Look At Testing’s Leading Edge


Mike Slessor, president and CEO of FormFactor, sat down with Semiconductor Engineering to discuss testing of AI and 5G chips, and why getting power into a chip for testing is becoming more difficult at each new node. SE: How does test change with AI chips, where you've got massive numbers of accelerators and processors developed at 7 and 5nm? Slessor: A lot of the AI stuff that we've been... » read more

Metrology Challenges For Gate-All-Around


Metrology is proving to be a major challenge for those foundries working on processes for gate-all-around FETs at 3nm and beyond. Metrology is the art of measuring and characterizing structures in devices. Measuring and characterizing structures in devices has become more difficult and expensive at each new node, and the introduction of new types of transistors is making this even harder. Ev... » read more

Making Chips At 3nm And Beyond


Select foundries are beginning to ramp up their new 5nm processes with 3nm in R&D. The big question is what comes after that. Work is well underway for the 2nm node and beyond, but there are numerous challenges as well as some uncertainty on the horizon. There already are signs that the foundries have pushed out their 3nm production schedules by a few months due to various technical issu... » read more

Power Management Becomes Top Issue Everywhere


Power management is becoming a bigger challenge across a wide variety of applications, from consumer products such as televisions and set-top-boxes to large data centers, where the cost of cooling server racks to offset the impact of thermal dissipation can be enormous. Several years ago, low-power design was largely relegated to mobile devices that were dependent on a battery. Since then, i... » read more

Moving To GAA FETs


How do you measure the size of a transistor? Is it the gate length, or the distance between the source and drain contacts? For planar transistors, the two values are approximately the same. The gate, plus a dielectric spacer, fits between the source and drain contacts. The contact pitch, limited by the smallest features that the lithography process can print, determines how many transistors ... » read more

5/3nm Wars Begin


Several foundries are ramping up their new 5nm processes in the market, but now customers must decide whether to design their next chips around the current transistor type or move to a different one at 3nm and beyond. The decision involves the move to extend today’s finFETs to 3nm, or to implement a new technology called gate-all-around FETs (GAA FETs) at 3nm or 2nm. An evolutionary step f... » read more

The Future Of FinFETs


The number of questions about finFETs is increasing—particularly, how long can they continue to be used before some version of gate-all-around FET is required to replace them. This discussion is confusing in many respects. For one thing, a 7nm finFET for TSMC or Samsung is not the same as a 7nm finFET for Intel or GlobalFoundries. There are a bunch of other nodes being proposed, as well, i... » read more