Week In Review: Design, Low Power

Synopsys acquires Silicon Frontline for electrical layout verification; CEVA buys spatial audio biz; verifying signals with digital twins; isolated gate driver; laser-based processing; chilly transistor models; racetrack connects qubits.


Synopsys acquired Silicon Frontline Technology, a provider of an electrical layout verification solution for mixed-signal and analog designs, large-scale power semiconductor devices, and electrostatic discharge protection networks. “This acquisition enables Synopsys to extend the capabilities of our design analysis portfolio and help build out a system-level electrical analysis platform. We also gain a robust framework that enables retargeting of the core engines for system-level signoff analysis of 3DICs, thermal, and electromigration,” said Hitesh Patel, senior director of product management for signoff solutions in the Synopsys EDA Group.

CEVA acquired the RealSpace 3D Spatial Audio business, technology, and patents from VisiSonics Corporation. The embedded software for headphones and earbuds recreates multi-channel spatial audio experience using two-channel stereo with support for dynamic head tracking.

IDTechEx projects that the global AI chips market will grow to $257.6 billion by 2033. It anticipates the three largest industry verticals in 2033 will be IT & Telecoms, Banking, Financial Services and Insurance (BFSI), and Consumer Electronics.

Silicon Catalyst is partnering with Arm on a contest for early-stage startup companies designing an SoC based on Arm processor IP. There is no restriction on the target application. The deadline to apply is June 23.

The CHIPS Act, as well as the ongoing need for talent, is causing both industry and academia in America to rethink engineering education, resulting in new interdisciplinary approaches and stronger partnerships to get students hands-on experience.

Products & tools

Keysight Technologies released a new Universal Signal Processing Architecture (USPA) prototyping platform. The platform enables pre-tapeout chip prototyping and verification in a real-time development environment integrating digital twins of fully compliant, standards-based signals. It supports high performance optoelectronic projects with digital-to-analog converter (DAC) and analog-to-digital converter (ADC) interfaces that emulate signals at full speed, up to 68 GS/s (ADC) and 72 GS/s (DAC). It also provides a broad range of input / output interfaces that are suitable for applications including 6G wireless development, digital radio frequency memory, advanced physics research, and high-speed data acquisition applications, such as radar and radio astronomy. Keysight also obtained FiRa Consortium validation for its automated ultra-wideband (UWB) PHY Conformance Test Tool, which can perform a range of UWB measurements including frequency, time, and amplitude domain analysis, as well as antenna characterization and system-level testing.

In a trio of stories, Semiconductor Engineering explores the role of AI and ML in chip design:

In recent weeks, the three largest EDA vendors have made sweeping announcements about incorporating machine learning into their tools at their respective user events, and the entire chip industry is heading in a similar direction. Machine learning, which teaches a machine how to perform a specific task based upon pattern recognition, is a natural fit for chip design. Reinforcement learning, which rewards behavior on a sliding scale and dynamically adjusts, is the primary method being deployed today.

A lot of excitement, and a fair amount of hype, surrounds what AI can do for the EDA industry. But many challenges must be overcome before AI can start designing, verifying, and implementing chips. Should AI replace the algorithms in use today, or does it have a different role to play?

Machine learning, deep learning, and AI increasingly are being used in chip design, and they are being used to design chips that are optimized for ML/DL/AI. The challenge is understanding the tradeoffs on both sides, both of which are becoming increasingly complex and intertwined.

Power devices

Infineon Technologies debuted the next generation of its dual-channel galvanically isolated gate driver ICs with configurable shoot-through protection (STP) and dead-time control (DTC). The product family spans multiple under-voltage lockout (UVLO) variants, isolation levels, and package options for applications including server and telecom SMPS, solar inverters and energy storage systems, motor drives and battery-powered applications, EV charging, and high-performance computing. Infineon also launched a 600 V GaN hybrid-drain-embedded gate injection transistor (HD-GIT) HEMT portfolio for various applications including industrial SMPS and consumer devices; a 40V MOSFET family for automotive applications; and new power modules using its 3.3 kV CoolSiC MOSFETs for high-power applications such as traction drive in trains.

The power consumption of a device is influenced by every stage of the design, development, and implementation process, but identifying opportunities to save power no longer can be just about making hardware more efficient. Huge opportunities remain for additional power and energy savings, but many of those involve questioning system-level decisions that have been blindly accepted for generations and many implementation nodes. Some of those decisions need to be reconsidered because they are preventing the construction of larger and more complex designs.

Onsemi released new 1200 V SiC fast-switching MOSFETs and half-bridge power integrated modules for automotive and industrial.

Cambridge GaN Devices uncorked a new series of 650 V gallium nitride HEMTs that use the company’s smart gate interface for improved overvoltage robustness, higher noise-immune threshold, dV/dt suppression, and ESD protection.

‍Nexperia released GaN FETs in e-mode (enhancement mode) configuration for low (100/150 V) and high (650 V) voltage applications.

Toshiba Electronic Devices & Storage Corporation launched high-speed quad-channel digital isolators that feature 100kV/μs (min) of high common mode transient immunity (CMTI) and a 150Mbps high-speed data rate.

Navitas Semiconductor uncorked SiC 650 V-rated Merged-PiN Schottky diodes for applications in server/telecom power supplies, industrial motor drives, solar inverters, LCD/LED TVs, and lighting.

Texas Instruments debuted a functional safety-compliant, isolated gate driver for traction inverters in EVs.


BOS Semiconductors licensed Arteris IP products for its next-generation automotive SoCs. Arteris FlexNoC interconnect IP will be used as the communication backbone, coupled with the Magillem Gold Suite for SoC integration automation.

FuriosaAI selected proteanTecs’ system health and performance monitoring data analytics solutions for use in its next-generation AI accelerators targeted at hyperscale data centers.

Quantum & HPC

LightSolver debuted what it calls a pure laser-based processing unit (LPU), a quantum-inspired solution that utilizes all-optical coupled lasers that require no electronics to compute. The company claims it is the size of a desktop computer with low power requirements and room temperature operation, but can compete with supercomputers and quantum computers in its ability to solve complex, NP-hard optimization problems in fields such as logistics, finance, and manufacturing.

Quantinuum introduced its latest quantum processor and accompanying system. The H2 processor features 32 fully-connected qubits and an ion trap with an oval shape resembling a racetrack, enabling each qubit to entangled with any other qubit in the system. In one of the first experiments conducted on the H2 system, scientists from Quantinuum, Harvard University, and Caltech demonstrated a novel state of matter, a non-Abelian topologically ordered state, and were able to control its properties in real time, including creation, braiding, and annihilation (measurement). It is possible that these non-Abelian anyons could be used to create topological qubits for future quantum computers.

The CryoCMOS Consortium created new, PDK-quality transistor models characterized for operation at both 4K and 77K cryogenic temperatures. The consortium selected the GlobalFoundries 22nm FDSOI (22FDX) process node, and transistor measurements were made by Incize. The transistor models, developed by SemiWise, include Typical-Typical (TT) transistors as well as corners (Slow-Slow, SS & Fast-Fast, FF). SureCore is using these to develop a suite of power-optimized foundation IP including standard cells, SRAM, ROM, and register files to enable the design of cryo-control ASICs for quantum computing. Funded by Innovate UK and led by sureCore, the consortium is working to develop quantum control systems that could be co-located with the qubits inside quantum computer’s cryostat, reducing the amount of cabling and complexity associated with having the control electronics outside the cryostat.

Google announced its Compute Engine A3 supercomputer, which is targeted for training large language models, diffusion models, and other models for generative AI. The A3 virtual machines combine eight NVIDIA H100 GPUs, 4th Gen Intel Xeon Scalable processors, and custom 200 Gbps infrastructure processing units (IPUs), with GPU-to-GPU data transfers bypassing the CPU host and flowing over separate interfaces from other VM networks and data traffic. The system also takes advantage of the company’s Jupiter data center networking fabric that scales to tens of thousands of highly interconnected GPUs and allows for full-bandwidth reconfigurable optical links that can adjust the topology on demand.

The Australian Government laid out a National Quantum Strategy to guide the country in quantum research and development, commercialization, creation of pipelines for investment in industry-ready quantum technologies, establishing materials supply chains and fabrication capabilities, and workforce development. Part of the effort will focus on building out quantum infrastructure, with the goal of creating an error-corrected quantum computer.

Samsung aims to develop a memory-centric supercomputer by 2028, according to a report from the Korea Herald.

IBM uncorked a set of capabilities to help organizations prepare for post-quantum security risks.

The University of Southern California announced a $1 billion initiative to promote computing education across all disciplines at the university. A focus of the effort will be on ethics in technology. It will also establish a new School of Advanced Computing for education and research in advanced computing technologies, including artificial intelligence and machine learning, data science, blockchain and quantum computing.

Research notes

Engineers from the University of Pennsylvania created a photonic device that provides programmable on-chip information processing without lithography. The device consists of spatially distributed optical gain and loss created by lasers that cast light directly on an unpatterned semiconductor wafer. The device is reconfigurable by tailoring the laser-cast patterns for optimal performance depending on the task. It can also be integrated with classical electronics.

Researchers at Columbia Engineering have developed a new class of integrated photonic devices they call ‘leaky-wave metasurfaces‘ that can convert light initially confined in an optical waveguide to an arbitrary optical pattern in free space. These devices provide simultaneous control of amplitude, phase, polarization ellipticity, and polarization orientation. Because the devices are thin, transparent, and compatible with photonic integrated circuits, the team envisions applications in optical displays, lidar, optical communications, and quantum optics.

A team from Cornell University developed an optical neural network (ONN) that can filter relevant information from a scene before the visual image is detected by a camera. Light coming through the sensor is processed through a series of matrix-vector multiplications, compressing the data at a ratio of up to 800-to-1 by discarding irrelevant or redundant information. In attempts to reconstruct the original image, the researchers found that while it didn’t replicate the original, the reconstruction did retain important features.

Upcoming events

  • ITF World 2023 – May 16-17 (Antwerp, Belgium)
  • Annual ESD Alliance Membership Meeting & CEO Outlook – May 18 (Santa Clara, CA)
  • International Memory Workshop – May 21-24 (Monterey, CA)
  • Embedded Vision Summit – May 22-24 (Santa Clara, CA)
  • RISC-V Summit Europe – June 5-9 (Barcelona, Spain)
  • Radio Frequency Integrated Circuits Symposium-RFIC 2023 – June 11-13 (San Diego, CA)
  • ISCA 2023: International Symposium on Computer Architecture – June 17-21 (Orlando, FL)
  • MIPI DevCon 2023: Mobile and Beyond – June 30 (San Jose, CA)
  • DAC 2023: Design Automation Conference – July 9-13 (San Francisco, CA)
  • More events and webinars

Further reading

Check out the latest Low Power-High Performance and Systems & Design newsletters for these highlights and more:

  • EDA Makes A Frenzied Push Into Machine Learning
  • True 3D-IC Problems
  • AI Adoption Slow For Design Tools
  • Designing For In-Circuit Monitors
  • RISC-V Driving New Verification Concepts
  • Holistic Power Reduction
  • Making Tradeoffs With AI/ML/DL
  • Rethinking Engineering Education In The U.S.

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