tag: Synopsys

Pushing Memory Harder
By Brian Bailey - 14 Oct, 2019 - Comments: 3

In an optimized system, no component is waiting for another component while there is useful work to be done. Unfortunately, this is not the case with the processor/memory interface. Put simply, memory cannot keep up. Accessing memory is slow, and it can consume a significant fraction of the power budget. And the general consensus is this problem is not going away anytime soon, despite effort... » read more

Week In Review: Design, Low Power
By Jesse Allen - 11 Oct, 2019 - Comments: 0

M&A Dialog Semiconductor will acquire Creative Chips for approximately $80 million cash, with contingent consideration of up to $23 million. The move will expand Dialog's Industrial IoT portfolio, adding Creative Chips' industrial Ethernet and other mixed-signal products for connecting large numbers of IIoT sensors to industrial networks. Based in Bingen, Germany, Creative Chips was founded in... » read more

Week in Review – IoT, Security, Autos
By Jeff Dorsch - 11 Oct, 2019 - Comments: 0

Products/Services Arm TechCon got under way with a series of announcements. Arm is a founding member of the Autonomous Vehicle Computing Consortium, along with General Motors, Toyota Motor, DENSO, Continental, Bosch, NXP Semiconductors, and Nvidia. More information on the consortium is available here. “Imagine a world where vehicles are able to perceive their dynamically changing environment... » read more

Shift Left Power-Aware Static Verification
By Himanshu Bhatt - 10 Oct, 2019 - Comments: 0

Next-generation SoCs with advanced graphics, computing, machine learning (ML) and artificial intelligence (AI) capabilities are posing new unseen challenges in Low Power Verification. These techniques can introduce critical bugs into a design, especially when the power-management infrastructure interacts with signals that cross clock or reset domains. This can create additional clock-domain cro... » read more

Focus Shifts To Wasted Power
By Brian Bailey - 10 Oct, 2019 - Comments: 0

Mobile phones made the industry aware of power, but now the focus is shifting to the total energy needed to perform a task. Activity that is unnecessary to perform the intended task is wasted power, and reducing it requires some new methodologies and structural changes within development teams. There is a broadening awareness about power. "The companies doing SoCs for mobile lead the charge ... » read more

Using Emulators For Power/Performance Tradeoffs
By Ann Steffora Mutschler - 10 Oct, 2019 - Comments: 0

Emulation is becoming the tool of choice for power and performance tradeoffs, scaling to almost unlimited capacity for complex chips used in data centers, AI/ML systems and smart phones. While emulation has long been viewed as an important but expensive asset for chipmakers trying to verify and debug chips, it is now viewed as an essential component for design optimization and analysis much ... » read more

Analyzing Testbench Design Performance Using Verdi Performance Analyzer
By Synopsys - 09 Oct, 2019 - Comments: 0

Performance continues to be key factor for the design of any complex system-on-chip (SoC). Moreover, complexity is increasing every day, which poses a challenge for engineers to track performance of the design, yet they are tasked to continuously increase chip performance. This paper describes the challenge to measure design performance and explains how Verdi Performance Analyzer enables run ti... » read more

Shrinking AV’s 1 Billion Test Miles
By Kevin Fogarty - 08 Oct, 2019 - Comments: 0

There is still no answer to how many miles an autonomous vehicle needs to drive before it's proven safe. But some AV developers and test companies are hoping to ease the burden a bit with automation that makes millions of real and simulated miles of road testing simpler to implement, supported by standards that make it easier to create and trade simulation scenarios. The goal is to reduce th... » read more

Week In Review: Design, Low Power
By Jesse Allen - 04 Oct, 2019 - Comments: 0

Synopsys completed its acquisition of QTronic GmbH, a provider of simulation, test tools, and services for automotive software and systems development. Terms of the deal were not disclosed. Synopsys launched the PrimeECO design closure solution, a signoff-driven solution that the company says achieves signoff closure with zero iterations. The tool includes a machine-learning-driven Hybrid Ti... » read more

Week in Review – IoT, Security, Autos
By Jeff Dorsch - 04 Oct, 2019 - Comments: 0

Products/Services Cadence Design Systems is working with Adesto Technologies to grow the Expanded Serial Peripheral Interface (xSPI) communication protocol ecosystem, for use in Internet of Things devices. The Cadence Memory Model for xSPI allows customers to ensure optimal use of the octal NOR flash with the host processor in an xSPI system, including support for Adesto’s EcoXiP octal xSPI ... » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2019 SMG   |  Terms of Service  |  Privacy Policy