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Designing Chips In A ‘Lawless’ Industry


The guideposts for designing chips are disappearing or becoming less relevant. While engineers today have many more options for customizing a design, they have little direction about what works best for specific applications or what the return on investment will be for those efforts. For chip architects, this is proving to be an embarrassment of riches. However, that design freedom comes wit... » read more

Week In Review: Design, Low Power


Tools Vtool released a new version of its Cogita visual debug platform. New features aim to provide faster debug capabilities, including visual representation of test results using log files as input, improved manipulation and navigation throughout big logs, ML algorithms to classify data and find the relationship between inputs, and the ability to merge and compare test flow of two different ... » read more

Week In Review: Auto, Security, Pervasive Computing


Automotive SGS-TÜV Saar certified that Cadence’s Tensilica Xtensa processors with FlexLock meets the ISO 26262:2018 standard to ASIL-D level. The new FlexLock feature is key to the certification because it supports lockstep, a fault-tolerant method that runs the same operation on two cores at the same time and then compares the output. Any difference in the output can be examined for issues... » read more

Challenges For New AI Processor Architectures


Investment money is flooding into the development of new AI processors for the data center, but the problems here are unique, the results are unpredictable, and the competition has deep pockets and very sticky products. The biggest issue may be insufficient data about the end market. When designing a new AI processor, every design team has to answer one fundamental question — how much flex... » read more

Sweeping Changes Ahead For Systems Design


Data centers are undergoing a fundamental change, shifting from standard processing models to more data-centric approaches based upon customized hardware, less movement of data, and more pooling of resources. Driven by a flood of web searches, Bitcoin mining, video streaming, data centers are in a race to provide the most efficient and fastest processing possible. But because there are so ma... » read more

Optimize Physical Verification Cost Of Ownership


As semiconductor designs continue to grow in size and complexity, they put increasing pressure on every stage of the design process. Physical verification, often on the critical path to tape-out, is especially affected. Design rule checking (DRC), layout versus schematic (LVS), and other physical verification runs take longer as chip size increases. In addition, finer geometries introduce new c... » read more

Continuous Education For Engineers


Continuous education is essential for engineers, but many companies don't recognize the value or they are unwilling to provide the necessary resources. This should be a line of questioning before every new hire makes the decision about where they want to work, because it not only affects their future career, but also impacts the value they can provide to that company during the course of the... » read more

Parallel RTL Exploration With Unparalleled Accuracy


Increasing chip complexity and restrictive advanced node rules have made it harder for implementation tools to achieve PPA targets and node entitlements via last-mile optimizations. RTL Architect enables designers to "shift-left" and predict the implementation impact of their RTL. RTL designers, SoC integrators, and IP developers have embraced this fast, predictive technology to give them new i... » read more

Blog Review: July 28


Synopsys' Chris Clark considers potential vulnerabilities in automotive over-the-air updates and best practices and new standards the industry can implement to improve security of vehicle software updates. Cadence's Paul McLellan gets a look at expected new fab construction in the coming years and where capacity is being focused. Siemens' Robin Bornoff dives into electromagnetic simulatio... » read more

Week In Review: Design, Low Power


Tools Cadence unveiled Cerebrus Intelligent Chip Explorer, a new machine learning-based tool to drive the Cadence RTL-to-signoff implementation flow. The tool aims to use reinforcement learning to find flow solutions that otherwise might not be explored and applies models to future designs. The company says it can improve productivity up to 10X and PPA up to 20% with optimization of the flow f... » read more

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