Chip Industry Week In Review

By The SE Staff - 08 Dec, 2023 - Comments: 0

By Jesse Allen, Karen Heyman, and Liz Allan AMD took the covers off new AI accelerators for training and inferencing of large language model and high-performance computing workloads. In its announcement, AMD focused heavily on performance leadership in the commercial AI processor space through a combination of architectural changes, better software efficiency, along with some improvements in... » read more

Security Becoming Core Part Of Chip Design — Finally

By Ann Mutschler - 07 Dec, 2023 - Comments: 0

Security is shifting both left and right in the design flow as chipmakers wrestle with how to build devices that are both secure by design and resilient enough to remain secure throughout their lifetimes. As increasingly complex devices are connected to the internet and to each other, IP vendors, chipmakers, and systems companies are racing to address existing and potential threats across a ... » read more

Why Are Automotive SoC Designers Turning To PCI Express 6.0?

By Richard Solomon - 07 Dec, 2023 - Comments: 0

Just over two decades ago, the introduction of PCI Express 1.0 marked the industry’s transition from then-ubiquitous parallel to serial interfaces. Back in 2002, the potential of “PCIe” in automotive applications was unforeseen – given the then-current state of in-vehicle computation and PCIe’s primary focus on desktop and data center use. Today, however, with the advent of connected ... » read more

AI Races To The Edge

By Karen Heyman - 07 Dec, 2023 - Comments: 0

AI is becoming increasingly sophisticated and pervasive at the edge, pushing into new application areas and even taking on some of the algorithm training that has been done almost exclusively in large data centers using massive sets of data. There are several key changes behind this shift. The first involves new chip architectures that are focused on processing, moving, and storing data more... » read more

Blog Review: Dec. 6

By Jesse Allen - 06 Dec, 2023 - Comments: 0

Cadence's Vinod Khera checks out potential implications of generative AI for EDA, including how it could increase the learning rate of students and reduce the rising verification cost. Synopsys' Kiran Vittal considers the driving factors behind RISC-V's growth and why it is becoming increasingly important for applications ranging from automotive to 5G mobile, AI, and data centers. Siemens... » read more

AI Accelerator Architectures Poised For Big Changes

By Ann Mutschler - 04 Dec, 2023 - Comments: 4

AI is driving a frenzy of activity in the chip world as companies across the semiconductor ecosystem race to include AI in their product lineup. The challenge now is how to make AI run faster, use less energy, and to be able to leverage it from the edge to the data center — particularly with the rollout of large language models. On the hardware side, there are two main approaches for accel... » read more

Chip Industry Week In Review

By The SE Staff - 01 Dec, 2023 - Comments: 0

By Susan Rambo, Gregory Haley, and Liz Allan Amkor plans to invest about $2 billion in a new advanced packaging and test facility in Peoria, Arizona. When finished, it will employ about 2,000 people and will be the largest outsourced advanced packaging facility in the U.S. The first phase of the construction is expected to be completed and operational within two to three years. Synopsys p... » read more

EDA Pushes Deeper Into AI

By Karen Heyman - 30 Nov, 2023 - Comments: 0

EDA vendors are ramping up the use of AI/ML in their tools to help chipmakers and systems companies differentiate their products. In some cases, that means using AI to design AI chips, where the number and breadth of features and potential problems is exploding. What remains to be seen is how well these AI-designed chips behave over time, and where exactly AI benefits design teams. And all o... » read more

3D-ICs May Be The Least-Cost Option

By Brian Bailey - 30 Nov, 2023 - Comments: 1

When 2.5D and 3D packaging were first conceived, the general consensus was that only the largest semiconductor houses would be able to afford them, but development costs are quickly coming under control. In some cases, these advanced packages actually may turn out to be the lowest-cost options. With stacked die [1], each die is considered to be a complete functional block or sub-system. In t... » read more

A Path To Increase Cell Utilization Rate And Decrease Routing Congestion In Chip Design Floorplanning

By Jim Schultz - 30 Nov, 2023 - Comments: 0

What do chip floorplanning and city planning have in common? As it turns out, quite a lot. This was the premise for an award-winning talk given by MediaTek at this year’s Synopsys User Group (SNUG) in Taiwan. Urban city development was used as an example to understand how utilization rate (UR) and congestion relate to chip planning. UR was defined in the example as population density while... » read more

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tag: Synopsys

Chip Industry Week In Review

Security Becoming Core Part Of Chip Design — Finally

Why Are Automotive SoC Designers Turning To PCI Express 6.0?

AI Races To The Edge

Blog Review: Dec. 6

AI Accelerator Architectures Poised For Big Changes

Chip Industry Week In Review

EDA Pushes Deeper Into AI

3D-ICs May Be The Least-Cost Option

A Path To Increase Cell Utilization Rate And Decrease Routing Congestion In Chip Design Floorplanning

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