tag: Siemens EDA

AI Data Centers And Auto Industry Converge On Same Issues
By Liz Allan - 02 Jul, 2026 - Comments: 0

Key Takeaways:   AI data centers need power from a range of sources, including batteries, to safeguard against blackouts, transient voltage spikes, and grid demand spikes.   As with regenerative braking and bidirectional charging in electric vehicles, data centers could feed power or heat back into the grid for public use, but the immediate goal is to disrupt the grid as little ... » read more

Accelerating Computational Lithography With GPU Rasterization
By Loay Hegazy - 02 Jul, 2026 - Comments: 0

By Loay Hegazy, Mohamed Taher, and Sherif Hammouda Semiconductor manufacturing at advanced nodes has become a race against physics. Even as feature sizes shrink, the tools that design and validate these circuits must operate with precision and speed. We show in a recent research paper that one part of the post-tapeout flow, rasterization, can be significantly sped up by deploying GPUs for ma... » read more

Observability Is A Missing Layer In AI-Era Chiplet Design
By Ann Mutschler - 01 Jul, 2026 - Comments: 0

Key Takeaways: In chiplet-based architectures, observability must be designed as a fabric-aligned, cross-die telemetry plane so architects can correlate traffic, latency, congestion, and fault behavior across package boundaries without losing system context. AI can extract value from high-volume silicon telemetry only when the architecture provides consistent instrumentation, near-senso... » read more

Blog Review: July 1
By Jesse Allen - 01 Jul, 2026 - Comments: 0

Cadence's Krunal Patel highlights auto-negotiation, a foundational feature in Ethernet that allows two connected devices to automatically determine the best possible operating parameters for a link, eliminating manual configuration and ensuring optimal performance. Synopsys' Sumit Vishwakarma warns of the rising cost of overdesign, particularly in advanced node and multi-die designs, and how... » read more

Rethinking Chip Verification
By Ann Mutschler - 29 Jun, 2026 - Comments: 0

Key Takeaways: AI and modern tools are easing traditional verification pain, but they're not addressing the underlying bottleneck in complex designs. Work is underway to create a golden, unambiguous spec above RTL, tracing requirements from spec to implementation to verification and checking for gaps, conflicts, and inconsistencies across levels and blocks, often with AI help. Tool c... » read more

Verification Methodologies Struggle To Keep Up With AI
By Brian Bailey - 25 Jun, 2026 - Comments: 0

Key Takeaways:  The rapid development of AI has resulted in new capabilities being provided to verification teams, beyond their ability to rationally insert them into accepted methodologies.  There is a lot of uncertainty about who will benefit the most from this technology. Is AI a junior engineer replacement or an enhancer?  The biggest benefits will come when AI helps engineers... » read more

Realizing The Future Of 3D-IC Design
By Keith Felton - 25 Jun, 2026 - Comments: 0

The integration of heterogeneous chiplet technology has fundamentally transformed semiconductor design, enabling the efficient creation of sophisticated system-in-packages by assembling pre-designed or third-party IP onto high-performance interposers and advanced packages. This approach offers significant advantages over traditional monolithic designs, including enhanced performance, improved p... » read more

Optimizing Curvilinear OPC: Vector- Based Site and Anchor Decoupling
By Siemens EDA - 24 Jun, 2026 - Comments: 0

As semiconductor technology advances to sub-5 nm nodes, curvilinear mask features are essential for pattern fidelity but challenge traditional OPC methods. Siemens introduces an advanced vector-based site and anchor decoupling framework that independently and dynamically controls OPC fragmentation and optimization. This innovation significantly boosts process window robustness, speeds up mask r... » read more

Blog Review: June 24
By Jesse Allen - 24 Jun, 2026 - Comments: 0

Cadence's Veena Parthan shows how finite element analysis simulations for crash testing can surpass the limitations of physical testing and offer insights into a wider array of crash scenarios that were once impossible to explore. Siemens' Haitham Eissa and Amr Khafagy warn that once-passive dummy fill structures have begun to influence design performance significantly as the industry progre... » read more

Designing Chips That Can Explain Themselves
By Ann Mutschler - 17 Jun, 2026 - Comments: 1

Key Takeaways: On-die telemetry gives architects a path to replace worst-case design margin with measured silicon behavior, improving PPA without compromising resilience. As monitor density and control-loop speed increase, observability must be architected hierarchically across local hardware response, on-die processing, and fleet-level learning. The real payoff is architectural: str... » read more

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