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Week In Review: Manufacturing, Test


Highlights from ITC The hot topic at this week’s International Test Conference (ITC) was tackling silent data corruption, with panel discussions, papers, and Google’s Parthasarathy Ranganathan’s keynote address all emphasizing the urgency of the issue. In the past two years Meta, Google, and Microsoft have reported on silent errors, errors not detected at test, which are adversely impact... » read more

Verification Methodologies Evolve, But Slowly


Semiconductor Engineering sat down to discuss digital twins and what is required to develop and verify new chips across a variety of industries, such as automotive and aerospace, with Larry Lapides, vice president of sales for Imperas Software; Mike Thompson, director of engineering for the verification task group at OpenHW; Paul Graykowski, technical marketing manager for Arteris IP; Shantanu ... » read more

Toward Domain-Specific EDA


More companies appear to be creating custom EDA tools, but it is not clear if this trend is accelerating and what it means for the mainstream EDA industry. Whenever there is change, there is opportunity. Change can come from new abstractions, new options for optimization, or new limitations that are imposed on a tool or flow. For example, the slowing of Moore's Law means that sufficient prog... » read more

Why Every Design IP Needs A Complete QA Methodology


Design IP is a key contributor to innovation in the semiconductor industry today. As the complexity and scale of silicon designs increase, so does design and verification time. Design IP enables modularization and re-use of design components, so that designers can leverage already-existing components as a baseline to accelerate design schedules. Therefore, it is not surprising that the usage of... » read more

Strengthening The Global Semi Supply Chain


This confluence of all these factors is creating disruptions around the globe. Compounding that, the end customer base is shifting from traditional chipmakers designing for a socket to a combination of systems companies, existing chipmakers, and a slew of new players that are developing chips for very specific applications. Some of those are being developed at the most advanced nodes, particula... » read more

Interactive Symmetry Checking Provides Faster, Easier Symmetry Verification For Analog And Custom IC Designs


Device symmetry ensures accurate, efficient performance of analog and custom IC designs. However, traditional physical verification for symmetry is complex and time-consuming. Calibre interactive symmetry checking runs inside the design environment to simplify and enhance IC symmetry verification. Design teams can use Calibre interactive symmetry checking to quickly and accurately analyze layou... » read more

How Memory Design Optimizes System Performance


Exponential increases in data and demand for improved performance to process that data has spawned a variety of new approaches to processor design and packaging, but it also is driving big changes on the memory side. While the underlying technology still looks very familiar, the real shift is in the way those memories are connected to processing elements and various components within a syste... » read more

How Mature Are Verification Methodologies?


Semiconductor Engineering sat down to discuss differences between hardware and software verification and changes and challenges facing the chip industry, with Larry Lapides, vice president of sales for Imperas Software; Mike Thompson, director of engineering for the verification task group at OpenHW; Paul Graykowski, technical marketing manager for Arteris IP; Shantanu Ganguly, vice president o... » read more

Minimizing EM/IR Impacts On IC Design Reliability And Performance


By Joel Mercier and Karen Chow As technologies and foundry process nodes continue to advance, it gets more difficult to design and verify integrated circuits (ICs). The challenges become even more apparent in 5nm and below nodes, and as the industry moves away from fin field-effect transistor (finFET) and into gate-all-around field-effect transistor (GAAFET) technologies. There are many prob... » read more

Rethinking Machine Learning For Power


The power consumed by machine learning is exploding, and while advances are being made in reducing the power consumed by them, model sizes and training sets are increasing even faster. Even with the introduction of fabrication technology advances, specialized architectures, and the application of optimization techniques, the trend is disturbing. Couple that with the explosion in edge devices... » read more

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