Author's Latest Posts

Optimizing Curvilinear OPC: Vector- Based Site and Anchor Decoupling
By Siemens EDA - 24 Jun, 2026 - Comments: 0

As semiconductor technology advances to sub-5 nm nodes, curvilinear mask features are essential for pattern fidelity but challenge traditional OPC methods. Siemens introduces an advanced vector-based site and anchor decoupling framework that independently and dynamically controls OPC fragmentation and optimization. This innovation significantly boosts process window robustness, speeds up mask r... » read more

Shift-left Schematic Memory Contention Analysis
By Siemens EDA - 11 Jun, 2026 - Comments: 0

Insight Analyzer streamlines memory block design by enabling early detection of memory contention at the schematic level. This shift-left approach lets design teams optimize architectures, mitigate risks and address reliability concerns before layout and manufacturing, helping to avoid costly rework and delays. Designers gain actionable analysis and clarity for complex memory block structures, ... » read more

A Comprehensive Approach To 3D-IC Physical Verification
By Siemens EDA - 05 Jun, 2026 - Comments: 0

3D integrated circuits (3D ICs) are reshaping semiconductor development. While these architectures deliver significant performance, power and integration gains, they introduce new challenges in verification—across electrical, thermal and mechanical domains. Siemens Calibre offers a comprehensive platform for 3D IC physical verification, linking DRC, LVS, advanced thermal simulation, mechanica... » read more

From Billions Of Violations To Actionable Insights: Calibre Vision AI
By Siemens EDA - 29 May, 2026 - Comments: 0

As advanced node SoCs increase in size and complexity, early full-chip DRC runs frequently produce hundreds of millions to billions of violations. This overwhelming scale leads to new challenges—not just in running checks, but in comprehending results, setting priorities, and coordinating closure across teams. Introduced in 2025, Calibre Vision AI enabled instance-complete, AI-guided triage a... » read more

ASIC Prototyping — New Design Realities Demand A New Approach
By Siemens EDA - 14 May, 2026 - Comments: 0

Modern ASIC design pushes prototypes to model vast RTL interactions across many FPGAs, often under high-bandwidth conditions that strain traditional systems. Verification teams also need fluid movement between emulation and at-speed prototyping, exposing any gaps in flow, tooling, or model continuity. This white paper presents an integrated solution that addresses these challenges through a uni... » read more

Enabling A Critical Phase in SoC Development
By Siemens EDA - 06 May, 2026 - Comments: 0

High speed execution of an SoC model on an FPGA-based prototyping system is essential—both to permit development and verification of the full software stack and to understand hardware/software interactions—before silicon is available. But for SoC designs that include high-speed, voluminous I/O, it is equally essential that the prototype be exercised with large amounts of real-world I/O o... » read more

Preparing For The Multiphysics Future of 3D ICs
By Siemens EDA - 01 Apr, 2026 - Comments: 0

3D integrated circuits (3D ICs) are emerging as a revolutionary approach to design, manufacturing and packaging in the semiconductor industry. Offering significant advantages in size, performance, power efficiency and cost, 3D ICs are poised to transform the landscape of electronic devices. However, with 3D ICs come new design and verification challenges that must be addressed to ensure success... » read more

Extraction Challenges of CFET and Backside Power Delivery
By Siemens EDA - 25 Mar, 2026 - Comments: 0

The integration of complementary field-effect transistors (CFETs) and buried power rails (BPRs) is central to advancing semiconductor scaling for nodes at 3nm and below. CFETs achieve unprecedented device density by vertically stacking n-type and p-type transistors, while BPRs embed the power network within the silicon substrate to boost efficiency and minimize area usage. These advances drive ... » read more

Human-Centered Agentic AI Workflows For RTL Verification
By Siemens EDA - 17 Mar, 2026 - Comments: 0

Productivity challenges in modern semiconductor development stem less from individual tool limitations and more from process-level complexity across design creation, verification, and iteration. Agentic EDA addresses this shift by embedding intelligence directly into workflows that span creation and validation. The Questa One Agentic Toolkit extends the Questa One solution with human-centere... » read more

The Future of Semiconductors: Engineering in the Convergence era
By Siemens EDA - 09 Mar, 2026 - Comments: 0

The semiconductor industry is entering a convergence era where silicon, software, physics, packaging, security, AI, and power constraints all intertwine. Device scaling still matters but architecture, integration, verification, and automation will define the industry’s trajectory. Organizations that embrace this cross-domain, lifecycle-oriented mindset will define the next decade. Moore’... » read more

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