Author's Latest Posts


High-Level Synthesis Enables The Next Generation Of Edge AI Accelerators


AI is becoming pervasive. But the ever increasing complexity is a challenge for IoT systems. Achieving the highest levels of performance and efficiency in edge AI means going beyond software and off the shelf hardware. Bespoke hardware accelerators in FPGA or ASICs can deliver much higher performance while consuming less energy. Building these accelerators with High-Level Synthesis slashes desi... » read more

Advancing Automotive Functional Safety Through Analog & Mixed-Signal Fault Simulation


The automotive industry is undergoing a major transformation, driven by the rise of electric vehicles, ADAS, connected cars, and autonomous vehicles. Due to the safety-critical nature of automotive applications, the reliability and tolerance to faults in semiconductor designs becomes paramount. This white paper delves into the role of analog fault simulation in the context of automotive functio... » read more

Reduce 3D-IC Design Complexity: Early Package Assembly Verification


Uncover the unique challenges, along with the latest Calibre verification solutions, for 3D-IC design in this new technical paper. As 2.5D and 3D-ICs redefine the possibilities of semiconductor design, discover how Siemens is leading the way in verifying complex multi-dimensional systems, while shifting verification left to do so earlier in the design process. What you'll learn: Overcom... » read more

Hybrid Methodology To Extract Kinetic And Magnetic Inductances For Superconductor Technologies


Integrated circuits (ICs) using superconductors have emerged as the technology of choice for artificial intelligence (AI), data centers, and cloud computing. However, innovative technology requires equally innovative physical verification solutions to ensure that these superconductor ICs deliver the performance and reliability they promise. We introduce an innovative hybrid methodology to extra... » read more

Paradigms Of Large Language Model Applications In Functional Verification


This paper presents a comprehensive literature review for applying large language models (LLM) in multiple aspects of functional verification. Despite the promising advancements offered by this new technology, it is essential to be aware of the inherent limitations of LLMs, especially hallucination that may lead to incorrect predictions. To ensure the quality of LLM outputs, four safeguarding p... » read more

Navigating Design Challenges


Explore the future of IC design with the Calibre Shift left initiative. In this paper, author David Abercrombie reveals how Siemens is changing the game for block/chip design-stage verification by moving Calibre verification and reliability analysis solutions further left in the design flow, including directly inside your P&R tool cockpit. Discover how you can reduce traditional long-loop v... » read more

Complex Safety Mechanisms Require Interoperability And Automation For Validation And Metric Closure


The race to autonomous mobility among the automobile manufacturers is driving the evolution of the underlying semiconductors. As a result, semiconductor technologies are moving towards higher densities and lower operating voltages, and this migration is introducing increasing sensitivity to random hardware failures – the failures which occur unpredictably over a semiconductor’s lifetime. Mo... » read more

A Game-Changer For IP Designers: Design-Stage Verification


Discover how to transform your IP design process with the Calibre Shift left initiative. In this new technical paper, you’ll gain valuable insights into how, by moving physical verification earlier in the IP design flow, you can locate and correct design errors sooner, reducing costs and getting complex designs to market faster. Dive into the challenges of hard, soft and custom IP creation, a... » read more

IC Package Physical Design Best Practices


Historically IC package design has been a relatively simple task which allowed the die bumps to be fanned out on a package substrate to a floorplan geometry suitable for connecting to a printed circuit board (PCB). But today the industry is moving to disaggregation of traditional monolithic SoC functions into chiplets often interfaced with local high-speed memory to avoid silicon reticle limits... » read more

Mastering Complexity Leveraging Digital Threads For Electronics Systems Design And Manufacturing


The rapid advancement of technology and its integration into various industries, particularly the electronics sector, has led to a significant increase in complexity. Digital threads offer a seamless framework for data flow throughout a product’s lifecycle, from ideation to utilization, fostering collaboration and informed decision-making. They intersect various domains, ensuring information ... » read more

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