Special Reports

Rethinking Chip Verification

By: Ann Mutschler

Specification engineering is gaining traction as a potential solution to the verification bottleneck.
Creating A Moore’s Law For AI Scaling

By: Laura Peters

Scaling AI becomes the grand challenge of the Intelligence Era.
Making On-Chip Photonics Manufacturable

By: Gregory Haley

AI systems are pulling optics closer to logic, but scalable manufacturing will require front-end fabrication, packaging, thermal management, materials, and...

 more »

Top Stories

I/O Design Challenges Grow In AI Data Centers And HPC Clusters

 Physical I/Os can be a chokepoint for high-performance chips and high-speed interconnec...
June 25th, 2026 By Liz Allan

Verification Methodologies Struggle To Keep Up With AI

 Engineers are flooded with new capabilities. The problem now is how best to deploy them.
June 25th, 2026 By Brian Bailey

Executive Outlook: Agentic AI’s Impact On Chip Design

 Can engineers trust AI to get everything right in semiconductor design and verification?
June 25th, 2026 By Ed Sperling

Mask Economics Shape High-NA EUV Adoption

 Rising mask costs, tighter high-NA requirements, and new materials challenges are forci...
June 22nd, 2026 By Gregory Haley

How To Build Billions of Bumps

 Hybrid bonding permits unprecedented connection density.
June 18th, 2026 By Bryon Moyer

GaN Power Devices Go Vertical

 Why new designs and process flows could help overcome manufacturing challenges.
June 18th, 2026 By Katherine Derbyshire

Designing Chips That Can Explain Themselves

 On-die monitors, localized analytics, and lifecycle data are giving architects new ways...
June 17th, 2026 By Ann Mutschler

Wi-Fi Flies Higher As Edge AI Build-Out Takes Root

 Chip and system designers scramble to leverage existing and future standards as edge AI...
June 15th, 2026 By Ed Sperling

Agentic AI Is Changing Data Center Architectures

 Standalone GPUs are being replaced by heterogeneous SoCs and chiplets that combine CPUs...
June 11th, 2026 By Ann Mutschler

Can AI Create Missing Models?

 It depends on what those models are used, which also can have a big impact on the cost.
June 11th, 2026 By Brian Bailey

PCIe Benefits From AI, Despite Scaling Protocols

 CXL is also gaining traction in AI processing, while MIPI and others are growing at the...
June 10th, 2026 By Bryon Moyer

AI Models Transform Defect Inspection And Review, But Can Fail To Scale

 Majority of AI initiatives falter; synthetic data gaining traction due to limited real-...
June 9th, 2026 By Laura Peters

Why Analog And Mixed-Signal Chips Resist Adaptive Test

 Analog behavior is difficult to compress into simple pass/fail decisions that could red...
June 9th, 2026 By Gregory Haley

Co-Packaged Optics Testing Faces Steep Data Center Ramp

 Scaling to tens of millions of CPO units per year requires the industry to first settle...
June 9th, 2026 By Anne Meixner

Orbital Data Centers Are Souped-Up Satellites – For Now

 Satellite constellations with extra onboard compute are several steps away from handlin...
June 4th, 2026 By Liz Allan

Keeping Security Algorithms Current Is Getting Harder

 As threats evolve faster, protecting security algorithms from design through manufactur...
June 4th, 2026 By Ann Mutschler

AI-Defined Vehicles Increase Pressure On Auto Ethernet Reliability

 Time-sensitive networking and MACsec allow Auto Ethernet to handle safety-critical func...
June 4th, 2026 By Liz Allan

GaN Power Devices Power Up

 New research points to safer devices with less loss at low voltages, but problems remai...
June 3rd, 2026 By Katherine Derbyshire

The Sub-2nm Paradox

 Reducing variation in manufacturing, monitoring behavior over time, and targeting speci...
June 1st, 2026 By Ed Sperling

Swapping Out Chiplets: I/Os Vs. Compute

 Multi-die assemblies give chip architects the option to change some dies while keeping ...
May 28th, 2026 By Liz Allan

more top stories »

Latest News

Chip Industry Week In Review

 Onsemi to buy Synaptics; IBM's 7Å chip w/40% more SRAM area; 1nm MoS2 nanotubes; AI pressure points; memory updates; $250M CHIPS Act award; trade secret theft; n...
June 26th, 2026 By The SE Staff

Blog Review: June 24

 Crash test dummies; dummy fill; de-risk development; network validation; sustainability roadmap.
June 24th, 2026 By Jesse Allen

Chip Industry Week In Review

 Apple-Intel is on, says Trump; Amkor's big win; Intel 18A-P; Amazon to sell its AI chips; Rambus' automotive RoT; Brewer's buy; VLSI Symposium tech; CHIPS Act fun...
June 19th, 2026 By The SE Staff

more news »



Opinion

CPO Will Dominate Scale-Up: Link Budgets For dB And $ Are Key

 Optical interconnects are needed to boost GPU throughput and u...
June 10th, 2026 By Geoff Tate

Disturbance In Verification

 We have started to see what may be the largest disturbance in ...
June 8th, 2026 By Brian Bailey

more opinions »



Research

Chip Industry Technical Paper Roundup: June 30

 Processing-using-DRAM interference; atomic-scale plasma proces...
By Linda Christensen

Research Bits: June 30

 Monolithic 3D integration; near-field heat transfer.
By Jesse Allen

Research Bits: June 23

 Redesigning high-NA EUV; embedded liquid cooling; light wavele...
By Jesse Allen

more research »



Startup Corner

Startup Funding: Q1 2026

 Massive rounds for AI, EDA, and manufacturing; 80 startups rai...
By Jesse Allen

Startup Funding: Q4 2025

 More and bigger funding rounds for AI chips and AI for making ...
By Jesse Allen

more startups »

Videos

How Far Left Can You Shift?

June 24th, 2026

New USB Standards: Benefits And Incompatibilities

June 23rd, 2026

Will Your Chip’s Memory Work As Expected?

June 22nd, 2026

Signoff Of Synthesis-Optimized Registers

June 17th, 2026

Knowledge Centers / Entities, people and technologies explored

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