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   Special Reports

The Path To Known Good Interconnects

By: Laura Peters

Heterogenous integration depends on reliable TSVs, microbumps, vias, lines, and hybrid bonds — and time to digest all the opt...
Will Floating Point 8 Solve AI/ML Overhead?

By: Karen Heyman

Less precision equals lower power, but standards are required to make this work.
Screening For Silent Data Errors

By: Anne Meixner

More SDEs can be found using targeted electrical tests and 100% inspection, but not all of them.

 more »

Top Stories

Power Issues Causing More Respins At 7nm And Below

Power may be the top reason why advanced chips are failing, but you have to look behind...

CXL Picks Up Steam In Data Centers

Market opportunities for shared resources balloon, but verification/validation remains ...

What Does 2023 Have In Store For Chip Design?

Many variables could shape the coming year, but it is the unknowns and how we react to ...

Choosing The Correct High-Bandwidth Memory

New applications require a deep understanding of the tradeoffs for different types of D...

Collaboration Widens Among Big Chip Companies

Top equipment and tools vendors see need for earlier cooperation as complexity rises fo...

Ferroelectric Memories: The Middle Ground

What is it, why is it important, and why now?

Unknowns And Challenges In Advanced Packaging

Promex's CEO looks at what works and what still needs to be fixed.

EV Architectures Evolving For Communication, Connectivity

But consensus on the best approach remains a moving target with complex tradeoffs.

Selecting The Right RISC-V Core

Ensuring that your product contains the best RISC-V processor core is not an easy decis...

Design And Verification Methodologies Breaking Down

As chips become more complex, existing tools and methodologies are stretched to the bre...

Growing System Complexity Drives More IP Reuse

But managing all the pieces is becoming more difficult with increasingly disaggregated ...

The Good And Bad Of Bi-Directional Charging

Challenges, possible solutions, and some intriguing economic models.

more top stories »

Latest News

Blog Review: Jan. 25

DDR5 design considerations; design, verification language adop...

EDA, IP Growth Surges Again

But not all regions show same level of strength as chip econom...

Week In Review: Semiconductor Manufacturing, Test

Dutch export restrictions; Foxconn fined by Taiwan; Lithuania...

Week In Review: Design, Low Power

Interoperable CDC verification; rapid signal integrity analysi...

more news »



Research

Research Bits: Jan. 24

Transistor-free compute-in-memory; neuromorphic computing with...

Research Bits: Jan. 17

Ionic circuit for neural nets; 3D printing MEMS sensors; quant...

Chip Industry’s Technical Paper Roundup: Jan. 17

Hardware trojans at four process technologies; eFPGAs; RISC-V ...

more research »



Startup Corner

Startup Funding: December 2022

Wafer manufacturing and GPUs draw investment; 106 companies ra...

more startups »

Videos

Multi-Die Integration


Efficient Trace In RISC-V


Silent Data Corruption


Why Matter 1.0 Really Matters

Knowledge Centers / Entities, people and technologies explored