System-Level Design

Top Stories

Do Parallel Tools Make Sense?
Experts at the Table, part 2: What can be done instead? And why are companies reluctant to do more in the cloud?
Published on August 10th,  2018 by Brian Bailey

Agile Standards
Standards development has changed from defining everything that might be nice, to a more Agile-like development process.
Published on August 8th,  2018 by Brian Bailey

Faster Verification With AI, ML
With engines improving, the design ecosystem is looking to new approaches to improve productivity.
Published on August 1st,  2018 by Ann Steffora Mutschler

Why Parallelization Is So Hard
Experts at the Table, part 1: Are we looking to solve the wrong problems? Where does parallelization work best and why.
Published on July 30th,  2018 by Brian Bailey

Debug Issues Grow At New Nodes
Finding the root cause of problems becoming more difficult as systemic complexity rises; methodology and different approaches play an increasingly ...
Published on July 26th,  2018 by Ann Steffora Mutschler

When Bugs Escape
The ability to find bugs has not kept up with the growing complexity of systems. Bugs are more likely to end up in products than ever before.
Published on July 26th,  2018 by Brian Bailey

Where ML Works Best
Cadence's president talks about machine learning inside and outside of EDA tools, and how to measure the benefits.
Published on July 26th,  2018 by Ed Sperling

Verification As A Flow
Experts at the Table, part 3: How will Portable Stimulus impact SoC verification and what adoption approaches are likely to catch on first?
Published on July 24th,  2018 by Brian Bailey

Design Reuse Vs. Abstraction
IP reuse has reduced the urgency for a higher level of abstraction in complex system-level design, but that still could change.
Published on July 5th,  2018 by Ann Steffora Mutschler

The Darker Side Of Consolidation
What happens when companies are combined? The outcome often isn't as good as the announcement.
Published on July 2nd,  2018 by Ed Sperling

More Top Stories »



Round Tables

Do Parallel Tools Make Sense?
Experts at the Table, part 2: What can be done instead? And why are companies reluctant to do more in the cloud?
Published on August 10th,  2018 by Brian Bailey

Faster Verification With AI, ML
With engines improving, the design ecosystem is looking to new approaches to improve productivity.
Published on August 1st,  2018 by Ann Steffora Mutschler

Why Parallelization Is So Hard
Experts at the Table, part 1: Are we looking to solve the wrong problems? Where does parallelization work best and why.
Published on July 30th,  2018 by Brian Bailey

Verification As A Flow
Experts at the Table, part 3: How will Portable Stimulus impact SoC verification and what adoption approaches are likely to catch on first?
Published on July 24th,  2018 by Brian Bailey

Verification As A Flow
Experts at the Table, part 2: How did Portable Stimulus get its name, and will it replace UVM?
Published on July 11th,  2018 by Brian Bailey

More Roundtables »



Multimedia

Changing The Design Flow
The rationale for fusing together various pieces of a digital design.
Published on August 7th,  2018 by Ed Sperling

High-Speed SerDes At 7nm
What's changing inside of data centers and how does it affect chip design?
Published on July 30th,  2018 by Ed Sperling

Will FPGAs Work As Expected?
Why equivalence checking is so critical for this market.
Published on July 27th,  2018 by Ed Sperling

M2M’s Network Impact
Why new architectures are required as machines begin talking to machines.
Published on July 25th,  2018 by Ed Sperling

ISO 26262 Statistics
Tech Talk: The statistical underpinnings of safety standards.
Published on July 2nd,  2018 by Ed Sperling

More Multimedia »



See All Posts in System-Level Design »

Latest Blogs

Editor's Note

Solving Systemic Complexity
The number of possible interactions is exploding. So why aren't tool companie...
July 26, 2018
by Ed Sperling
What Were They Thinking

A New Era For EDA
Is EDA in decline? Will its fortunes turn around with the end of Moore's Law?
by Brian Bailey
Just A Formality

Functional Safety: Art Or Science?
The market for safety-critical electronics is booming, but development practi...
by Sergio Marchese
Frankly Speaking

The Future Is Bright: DARPA Is Driving Electronic Resurgence
Revisiting old ideas leads to new paths forward as changes in technology, arc...
by Frank Schirrmeister
Semi Thoughts

Technical Conferences: The Insurmountable Opportunity
The number of new markets makes it difficult to choose between an expanding a...
by Mike Gianfagna
Looking Past The Horizon

“Good Enough For Government Work?” Not Anymore.
For more precise static timing analysis with less uncertainty, rethink the id...
by Ruben Molina
A System Perspective

Synthesizing Computer Vision Designs To Hardware
Traditional RTL design flows aren't a good fit for the rapidly changing requi...
by Mike Fingeroff
Design & Verification

PCIe In High-Performance FPGAs
The value of high performance computing applications depends upon how fast da...
by Vatsal Choksi
Intelligent Analytics

Bugs With Long Tails Can Be Costly Pests
In the world of servers and HPC, the smallest of inefficiencies can build int...
April 26, 2018
by Gajinder Panesar
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Looking For The Elephant In The Valley
Female role models doing exceptional things in tech have always existed. Hope...
March 27, 2018
by Kavya Ram Mohan
Against The Grain

Abstracting Abstracter Abstractions In Functional Verific...
With the upcoming Portable Stimulus standard, we need to consider whether abs...
March 26, 2018
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