Systems & Design

Top Stories

AI In Chip Design: Tight Control Required
Why and where limitations are needed in AI-driven design, and where software-defined hardware works best.
Published on July 16th, 2025 by Ed Sperling

Startup Funding: Q2 2025
New architectures and manufacturing methods draw investors; 75 startups raise $1.9 billion.
Published on July 14th, 2025 by Jesse Allen

Mixed Messages Complicate Mixed-Signal
Analog and mixed signal content is adding risk to ASIC designs. Pessimists see the problem getting worse, while optimists point to AI and chiplets ...
Published on June 26th, 2025 by Brian Bailey

Distributing Intelligence Inside Multi-Die Assemblies
Disaggregration requires traffic cops and in-chip monitors to function as expected over time.
Published on June 26th, 2025 by Ed Sperling

Security Vulnerabilities Difficult To Detect In Verificat...
New tools and techniques are being developed and can help keep the verification process secure, alongside a firm foundation of good design verifica...
Published on June 26th, 2025 by Ann Mutschler

Can You Build A Known-Good Multi-Die System?
Executive Outlook: Just because the various components in an advanced package work individually and together doesn't guarantee they will work post-...
Published on June 18th, 2025 by Ed Sperling

Optimizing Data Movement
Problems and solutions for improving performance with more data.
Published on May 29th, 2025 by Ann Mutschler

A Balanced Approach To Verification
In the past, simulation was the only tool available for verification, but today there are many. Balancing the costs and rewards is not always easy.
Published on May 29th, 2025 by Brian Bailey

Executive Outlook: Chiplets, 3D-ICs, and AI
Trouble spots, and some fixes, for the next wave of high-performance semiconductors.
Published on May 29th, 2025 by Ed Sperling

More Data, More Redundant Interconnects
Circuits are being pushed harder and longer, particularly with AI, speeding up the aging of data paths. Photonics adds its own complications.
Published on May 19th, 2025 by Ed Sperling

More Top Stories »



Round Tables

AI In Chip Design: Tight Control Required
Why and where limitations are needed in AI-driven design, and where software-defined hardware works best.
Published on July 16th, 2025 by Ed Sperling

Can You Build A Known-Good Multi-Die System?
Executive Outlook: Just because the various components in an advanced package work individually and together doesn't guarantee they will work post-...
Published on June 18th, 2025 by Ed Sperling

Executive Outlook: Chiplets, 3D-ICs, and AI
Trouble spots, and some fixes, for the next wave of high-performance semiconductors.
Published on May 29th, 2025 by Ed Sperling

From Tool Agents To Flow Agents
The industry has already demonstrated gains using AI in tight iteration loops, but how does that evolve to cover larger portions of the development...
Published on April 30th, 2025 by Brian Bailey

AI Agents Need Goals
AI cannot optimize unless it can measure progress towards goals, but defining those goals is not easy, especially when looking at the entire develo...
Published on April 16th, 2025 by Brian Bailey

More Roundtables »



Multimedia

Agentic AI In Chip Design
What comes next after generative AI, and how that will be used in EDA.
Published on June 11th, 2025 by Ann Mutschler

Optical Interconnectivity At 224 Gbps
Pros and cons of replacing copper with optical in data-intensive AI systems.
Published on May 28th, 2025 by Ed Sperling

Speeding Up Die-To-Die Interconnectivity
Just adding more or thicker wires to a design isn't sufficient with chiplets.
Published on May 14th, 2025 by Ed Sperling

What’s Changing In SerDes
Faster data movement in AI systems comes at a cost.
Published on April 16th, 2025 by Ed Sperling

Optimizing Data Movement In SoCs And Advanced Packages
Managing on-chip data is becoming more challenging in the AI era.
Published on March 18th, 2025 by Ed Sperling

More Multimedia »



See All Posts in System-Level Design »

Latest Blogs

First By Design

Democratizing Design: How The CHIPS Act Is Reshaping EDA ...
Reflections from a recent panel discussion at DAC, The Chips to Systems Confe...
July 2, 2025
by Nilesh Kamdar
A System Perspective

Rethinking Chip Debug
Complexity demands a smarter solution.
June 30, 2025
by Priyank Jain
Intelligent System Design

Redefining SoC Design: The Shift To Secure Chiplet-Based ...
Ensuring trusted execution across multiple chiplets and vendors is more compl...
June 26, 2025
by Moshiko Emmer
The Next Wave

Programmable Hardware Delivers 10,000X Improvement In Ver...
How FPGAs can be used to identify bursts of errors in wireline networking and...
June 26, 2025
by Tony Chan Carusone
Looking Past The Horizon

Closing The RISC-V Verification Disconnect
Plan for multiple complementary verification methodologies for different leve...
May 29, 2025
by Larry Lapides
NoC NoC

CSR Management: Life Beyond Spreadsheets
Eliminating hardware-software mismatches and ensuing design re-spins with an ...
May 29, 2025
by Insaf Meliane
Making Formal Normal

How To Optimize Silicon Utilization To Improve PPA
As designs grow more complex, detecting and eliminating underutilized compone...
April 29, 2025
by Ashish Darbari
Memory/IO Wall Solutions

AI Infrastructure At A Crossroads
Weighing efficiency gains vs. the scale of personalization.
January 30, 2025
by Ramin Farjadrad
The Chiplet Connection

Enabling Innovative Multi-Vendor Chiplet-Based Designs
What makes chiplets so attractive, and why they are essential for future desi...
September 26, 2024
by Elad Alon
Clock Talk

Droop And Silent Data Corruption
Advanced silicon lifecycle analytics and on-die telemetry are needed to count...
July 25, 2024
by Aakash Jani

Knowledge Centers
Entities, people and technologies explored


  Trending Articles

Power Delivery Challenges For AI Chips
Rising power densities and new architectures are forcing a rethinking of interconnects, materials, and thermal management.
by Gregory Haley

Novel Assembly Approaches For 3D Device Stacks
ECTC progress report on enabling technologies, including cooling chiplets, 1µm hybrid bonding, RDL buildups, and co-packaged optics.
by Laura Peters

Startup Funding: Q2 2025
New architectures and manufacturing methods draw investors; 75 startups raise $1.9 billion.
by Jesse Allen

Chip Industry Week in Review
$60B fab buildout; Chinese automakers tout 100% homemade chips; 2nm custom SRAM; Cadence's virtual platform buy; multi-chiplet NoC; HBM roadmap; MIT's GaN fab technique; 30% tax credit; Taiwan export restrictions, power vulnerability; global memory market; rad-tolerant memory; 2D, non-silicon computer.
by The SE Staff

EDA’s Top Execs Map Out An AI-Driven Future
AI is accelerating the need for 3D-ICs and digital twins, and causing lots of disruption along the way.
by Ed Sperling

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