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Systems & Design

Top Stories

Challenges For New AI Processor Architectures
Getting an AI seat in the data center is attracting a lot of investment, but there are huge headwinds.
Published on July 29th,  2021 by Brian Bailey

Sweeping Changes Ahead For Systems Design
Demand for faster processing with increasingly diverse applications is prompting very different compute models.
Published on July 29th,  2021 by Ann Steffora Mutschler

Continuous Education For Engineers
Companies that invest in their employees' education often get rewarded with more productive and happier workers.
Published on July 29th,  2021 by Brian Bailey

CEO Outlook: Chiplets, Longer IC Lifetimes, More End Markets
How the end of scaling and the electrification of everything are changing chip design.
Published on July 14th,  2021 by Ed Sperling

Debug: The Schedule Killer
Time spent in debug is unpredictable. It consumes a large portion of the development cycle and can disrupt schedules, but good practices can minimi...
Published on June 30th,  2021 by Brian Bailey

Rocky Road To Designing Chips In The Cloud
The EDA ecosystem is in the early stages of pivoting to the cloud, but not everything will move there.
Published on June 24th,  2021 by Ann Steffora Mutschler

Architectural Considerations For AI
What will it take to be successful with a custom chip for processing a neural network targeting the data center or the edge? A lot of money is look...
Published on June 24th,  2021 by Brian Bailey

CEO Outlook: More Data, More Integration, Same Deadlines
How design is changing with the shift from homogeneous ICs to heterogeneous, multi-chip packages.
Published on June 24th,  2021 by Ed Sperling

Continuing Challenges For Open-Source Verification
Is there an open-source business model that works for verification and debug?
Published on June 1st,  2021 by Brian Bailey

Do We Have An IC Model Crisis?
Models enable automation and optimization, but today the need for new and more complex models is outstripping the ability to ratify and standardize...
Published on May 27th,  2021 by Brian Bailey

More Top Stories »



Round Tables

CEO Outlook: More Data, More Integration, Same Deadlines
How design is changing with the shift from homogeneous ICs to heterogeneous, multi-chip packages.
Published on June 24th,  2021 by Ed Sperling

Continuing Challenges For Open-Source Verification
Is there an open-source business model that works for verification and debug?
Published on June 1st,  2021 by Brian Bailey

Standards, Open Source, and Tools
EDA has been more successful creating open languages and standards rather than promoting open-source collaboration. Will this change?
Published on May 10th,  2021 by Brian Bailey

New Methodologies Create New Opportunities
Does RISC-V processor verification provide common ground to develop a new verification methodology, and will that naturally lead to new and potenti...
Published on April 27th,  2021 by Brian Bailey

How Heterogeneous ICs Are Reshaping Design Teams
Increasingly complex systems are creating much different relationships between engineering specialities.
Published on March 31st,  2021 by Ed Sperling

More Roundtables »



Multimedia

EDA In The Cloud
Is it technology or business models that are holding this back?
Published on June 9th,  2021 by Ann Steffora Mutschler

Next-Gen SerDes Roadmap
What’s new, what’s changed, and why.
Published on May 25th,  2021 by Ed Sperling

Next-Gen Design Challenges
Converging workflows to deal with the intersection of rising system and scale complexity.
Published on April 20th,  2021 by Ed Sperling

Better Quality RTL
How to boost efficiency in chip design.
Published on February 2nd,  2021 by Ann Steffora Mutschler

High-Speed SerDes At 7/5nm
How to place macros inside a PHY in 7/5nm SoCs.
Published on June 2nd,  2020 by Ed Sperling

More Multimedia »



See All Posts in System-Level Design »

Latest Blogs

What Were They Thinking

Rethink, Not Replicate
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by Brian Bailey
Frankly Speaking

Choosing The Right Model Fidelity For Your Digital Twin
Automatically developing the most appropriate model and its fidelity for a gi...
by Frank Schirrmeister
Lost Art Of Processor Verification

RISC-V Verification: The 5 Levels Of Simulation-Based Pro...
The design freedoms of RISC-V offer developers flexibility for innovation –...
by Lee Moore
A System Perspective

Robust Variation-Aware Smart Power Designs For Silicon Su...
Using machine learning to enable fast and accurate high-sigma analysis.
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Looking Past The Horizon

Optimize Physical Verification Cost Of Ownership
Minimize unused compute resources during DRC and LVS runs.
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Just A Formality

Formally Verifying SystemC/C++ Designs
As the level of abstraction increases, so too must the level of verification.
by Rob van Blommestein
Embedded Customization

Is RISC-V The Future?
Barriers between processor types are breaking down and more complex, higher p...
by Roddy Urquhart
Design & Verification

Developing A Real-Time SDR System
Implementing software-defined radio by integrating a tool like GNU Radio with...
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Rule The Bugs

Invent A New Way To Do Your Job
While the fundamentals of good engineering remain the same, it's worth trying...
May 27, 2021
by Hagai Arbel
RISC-V Design Verification

An Insider’s View Of Verifying Custom RISC-V Proces...
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March 15, 2021
by Shubhodeep Roy Choudhury
Editor's Note

The Next Wave Of Consolidation
Economic conditions are all there. So what's the holdup?
September 28, 2020
by Ed Sperling

Knowledge Centers
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