Systems & Design

Top Stories

Silo Busting In The Design Flow

Waterfall development flows no longer work for chip design, but unified tool flows may not be the answer.

Using AI And Bugs To Find Other Bugs

New methodologies are being developed to deal with increasing complexity.

Brute-Force Analysis Not Keeping Up With IC Complexity

How to ensure you've dealt with the most important issues within a design, because finding those spots is becoming a lot more important.

Speeding Up AI With Vector Instructions

Uses, challenges and tradeoffs in working with vector engines.

Using Verification Data More Effectively

There are more tips and tricks than ever to get the most from verification.

Is Hardware-Assisted Verification Avoidable?

Simulation is no longer up to the task of system-level verification, but making the switch to hardware-assisted verification can lead to some surpr...

RISC-V: Will There Be Other Open-Source Cores?

Experts at the Table: The current state of open-source tools, and what the RISC-V landscape will look like by 2025.

System-Level Packaging Tradeoffs

Growing complexity is creating an array of confusing options.

Deals That Change The Chip Industry

Nvidia-Arm is just the beginning; more acquisitions are on the horizon.

Have Processor Counts Stalled?

Have chips reached a plateau for the number of processor cores they can effectively make use of? Possibly yes, until you change the programming model.

More Top Stories »



Round Tables

RISC-V: Will There Be Other Open-Source Cores?

Experts at the Table: The current state of open-source tools, and what the RISC-V landscape will look like by 2025.

RISC-V: What’s Missing And Who’s Competing

Experts at the Table: The open-source ISA is gaining ground in multiple markets, but the tool suite is incomplete and the business model is uncertain.

Creating Better Models For Software And Hardware Verifica...

Experts at the Table: Rethinking approaches for more complex systems, ISAs, and chiplets.

RISC-V Gaining Traction

Experts at the Table: Extensible instruction-set architecture is drawing attention from across the industry and supply chain.

Chip Reliability Vs. Cost

CEO Outlook: Market shifts, higher productivity per engineer and the overhead and opportunities for security and reliability.

More Roundtables »



Multimedia

High-Speed SerDes At 7/5nm

How to place macros inside a PHY in 7/5nm SoCs.

Rising Packaging Complexity

Why advanced packaging is still so difficult.

Speeding Up Verification Using SystemC

How HLS plus formal can significantly reduce optimization and debug time.

Timing Closure At 7/5nm

Why shifting left in a complex design is critical.

Banking On FPGA Prototyping

Where the biggest savings are in ASIC design.

More Multimedia »



See All Posts in System-Level Design »

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Knowledge Centers
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Dealing With Security Holes In Chips

Challenges range from constant security updates to expected lifetimes that last beyond the companies that made them.

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Rising costs, complexity, and fuzzy delivery schedules are casting a cloud over next-gen lithography.

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