System-Level Design

Top Stories

The Role Of EDA In AI
Experts at the Table, part 3: Which aspects of AI implementation should EDA create tools for?
Published on April 17th,  2019 by Brian Bailey

From AI Algorithm To Implementation
Experts at the Table, part 2: The transformation from algorithm to implementation has some significant problems that are not being properly address...
Published on April 10th,  2019 by Brian Bailey

Big Shift In Multi-Core Design
System-wide concerns in AI and automotive are forcing hardware and software teams to work together, but gaps still remain.
Published on April 3rd,  2019 by Ann Steffora Mutschler

Heterogeneous Design Creating Havoc With Firmware Versions
Updates, last-minute changes to design add a whole new set of challenges at sign-off.
Published on April 1st,  2019 by Ed Sperling

Digital Twins Deciphered
It’s easy to see a digital twin as nothing more than a simulation model, but that would ignore a very important difference.
Published on March 28th,  2019 by Brian Bailey

Utilizing More Data To Improve Chip Design
Different ways of collecting, analyzing and applying that data to improve efficiency and reliability.
Published on March 28th,  2019 by Ann Steffora Mutschler

The Automation Of AI
Experts at the Table, part 1: Will the separation of hardware and software for AI cause problems and how will hardware platforms for AI influence a...
Published on March 28th,  2019 by Brian Bailey

Data-Driven Verification Begins
Experts at the Table: What determines good vs. bad data, why the EDA industry is so slow to catch on, and what verification engineers are really lo...
Published on March 27th,  2019 by Ed Sperling

The Other Side Of Makimoto’s Wave
Custom design is gaining ground against standardized approaches in a variety of new applications.
Published on March 6th,  2019 by Ann Steffora Mutschler

New Design Approaches At 7/5nm
Smaller features and AI are creating system-level issues, but traditional ways of solving these problems don't always work.
Published on March 4th,  2019 by Ed Sperling

More Top Stories »



Round Tables

The Role Of EDA In AI
Experts at the Table, part 3: Which aspects of AI implementation should EDA create tools for?
Published on April 17th,  2019 by Brian Bailey

The Automation Of AI
Experts at the Table, part 1: Will the separation of hardware and software for AI cause problems and how will hardware platforms for AI influence a...
Published on March 28th,  2019 by Brian Bailey

Data-Driven Verification Begins
Experts at the Table: What determines good vs. bad data, why the EDA industry is so slow to catch on, and what verification engineers are really lo...
Published on March 27th,  2019 by Ed Sperling

Partitioning Drives Architectural Considerations
Experts at the Table, part 2: Biggest tradeoffs in partitioning.
Published on February 25th,  2019 by Ann Steffora Mutschler

Making IP Friendlier
Experts at the Table, part 2: Some IP issues remain unsolved even after 20 years. What the IP industry needs to change for growth.
Published on December 27th,  2018 by Brian Bailey

More Roundtables »



Multimedia

Billion-Gate Design Connectivity
Dealing with integration issues in large, complex chips.
Published on March 27th,  2019 by Ed Sperling

Debug Changes At Advanced Nodes
Why traditional verification methods are becoming less effective.
Published on March 27th,  2019 by Ed Sperling

New Memory Options
Using data as the starting point for designs opens up new architectural choices.
Published on February 28th,  2019 by Ed Sperling

Reverse Debug
How to reduce time spent on debugging complex chips.
Published on February 28th,  2019 by Ed Sperling

More Than A Core
A system-level look at integration, security, and new architectures such as RISC-V.
Published on December 20th,  2018 by Ann Steffora Mutschler

More Multimedia »



See All Posts in System-Level Design »

Latest Blogs

Editor's Note

Auto Reliability At The System Level
Why different starting points and definitions could have a big impact on auto...
March 28, 2019
by Ed Sperling
What Were They Thinking

The Value Of A Model
How much would you pay for a model? Recently, the answer to that has been $$$.
by Brian Bailey
Just A Formality

Fibonacci And Honey Bees Have Something In Common: A Swee...
Can assertions enable engineers to design IP that is correct by construction?
by Sergio Marchese
Frankly Speaking

Digital Twins For Hardware/Software Co-Development
Properly defining what digital twins are is an important part of determining ...
by Frank Schirrmeister
Looking Past The Horizon

Building Bridges: A New DFT Paradigm
Greater complexity and smaller process nodes are driving a major shift in des...
by Synopsys
Programmed Complexity

Getting A Complete Picture Of Automotive Software
How tools can help address complex automotive software architectures efficien...
by Maximilian Odendahl
A System Perspective

How Qualcomm Got Faster Signoff DRC Convergence
A case study on improving DRC during base layers tapeout and managing IP inte...
by Srinivas Velivala
Design & Verification

Of Aero Shows And Safety
As DO-254 approaches its 19th birthday, it's time to look beyond just using b...
by Janusz Kitel
Semi Thoughts

High-Speed Communications: On The Road Again
Showing off long-reach SerDes over a five-meter cable.
by Mike Gianfagna
Intelligent Analytics

RISC-V At Embedded World
The rapidly-growing embedded conference covers a range of sectors and applica...
by Jo Windel
Against The Grain

Make-Or-Break Time For Portable Stimulus
We hear a lot from vendors about the new Portable Stimulus Standard, but how ...
October 25, 2018
by Neil Johnson

Knowledge Centers
Entities, people and technologies explored


  Trending Articles

Making Chip Packaging Simpler

The promise of advanced packaging is being able to integrate heterogeneous chips, but a lot of work is needed to make that happen.

by Ed Sperling and Mark LaPedus

EUV Arrives, But More Issues Ahead

Improvement still needed for uptime, defectivity, line edge roughness and process flows.

by Katherine Derbyshire

Single Vs. Multi-Patterning EUV

Why this choice isn’t as obvious as it might look.

by Mark LaPedus

The 7nm Pileup

Why are so many companies rushing to do 7nm designs?

by Ed Sperling

3D NAND Metrology Challenges Growing

Rising costs and gaps in equipment emerge as technology scales; new tools under development.

by Mark LaPedus

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