Systems & Design

Top Stories

Why It’s So Hard To Create New Processors
Many companies are interested in developing their own processors, following the success of RISC-V, but verification is a daunting challenge.
Published on March 26th,  2020 by Brian Bailey

Software-Defined Hardware Gains Ground — Again
AI applications are prompting chipmakers to take another look at different options for reconfigurable hardware.
Published on March 26th,  2020 by Ann Steffora Mutschler

Do You Trust Your IP Supplier?
How secure is the IP that you are integrating into your system? Accellera wants to help with that.
Published on March 26th,  2020 by Brian Bailey

3nm: Blurring Lines Between SoCs, PCBs And Packages
The end of Moore's Law is providing options for shifting what goes where and how it gets designed.
Published on March 2nd,  2020 by Ann Steffora Mutschler

An Increasingly Complicated Relationship With Memory
Pressure is building to change the programming paradigm associated with memory, but so far economic justifications have held back progress.
Published on February 27th,  2020 by Brian Bailey

The Challenges Of Building Inferencing Chips
As the field of AI continues to advance, different approaches to inferencing are being developed. Not all of them will work.
Published on February 27th,  2020 by Ann Steffora Mutschler

The Cost Of Programmability
How much flexibility should be incorporated in a chip and at what level should it be programmable? Those questions are getting more complicated.
Published on February 27th,  2020 by Brian Bailey

Design For Airborne Electronics
Safety, security and traceability are required in avionics, but more complex chips are exposing gaps in the tool chain and in engineer training.
Published on February 3rd,  2020 by Ann Steffora Mutschler

Divided On System Partitioning
How close can we get to automated system optimization from a software function? The target keeps moving but the tools keep becoming more capable.
Published on January 30th,  2020 by Brian Bailey

Making Sure RISC-V Designs Work As Expected
Open-source growth predictions are impressive, but the verification process can be harder than with commercial ISAs.
Published on January 30th,  2020 by Ann Steffora Mutschler

More Top Stories »



Round Tables

Portable Stimulus And Digital Twins
Experts at the Table: How Portable Stimulus plays with the digital twin and the drive toward system-level coverage.
Published on November 25th,  2019 by Brian Bailey

RISC-V Markets, Security And Growth Prospects
Experts at the Table: Why RISC-V has garnered so much attention, what still needs to be done, and where it will likely find its greatest success.
Published on November 18th,  2019 by Ed Sperling

Migrating 3D Into The Mainstream
Experts at the Table: The creation of complex, packaged systems affects everything in the design flow and requires a systems approach.
Published on October 31st,  2019 by Brian Bailey

RISC-V Challenges And Opportunities
Who makes money with an open-source ISA, the current state of the RISC-V ecosystem, and what differentiates one vendor from the next.
Published on October 24th,  2019 by Ed Sperling

Extending Portable Stimulus
Experts at the Table: With the initial standard in place, what can we expect in terms of broadening its scope to other domains and applications?
Published on October 16th,  2019 by Brian Bailey

More Roundtables »



Multimedia

Speeding Up Verification Using SystemC
How HLS plus formal can significantly reduce optimization and debug time.
Published on March 23rd,  2020 by Ed Sperling

Timing Closure At 7/5nm
Why shifting left in a complex design is critical.
Published on March 17th,  2020 by Ed Sperling

Banking On FPGA Prototyping
Where the biggest savings are in ASIC design.
Published on March 4th,  2020 by Ed Sperling

Fusing Implementation And Verification
Re-using Tcl scripts to reduce cost and potential errors.
Published on March 2nd,  2020 by Ed Sperling

Speeding Up FPGA Development
How to debug a large FPGA design.
Published on February 28th,  2020 by Ed Sperling

More Multimedia »



See All Posts in System-Level Design »

Latest Blogs

Editor's Note

What’s Changing, What Isn’t
The overall chip industry remains healthy, with some caveats.
March 26, 2020
by Ed Sperling
What Were They Thinking

Standard Evolution
More end-user involvement means a different approach to standardization.
by Brian Bailey
Looking Past The Horizon

Physical Verification For Photonics Integrated Circuits
While promising for a range of networking applications, photonic ICs present ...
by Manoz Palaparthi
Frankly Speaking

Making Sense Of EDA And Digital Twins
How does the digital twin translate to different industries?
by Frank Schirrmeister
Just A Formality

GapFree Processor Verification
Applying formal verification to thoroughly verify a RISC-V processor design.
by Tom Anderson
A System Perspective

EDA In The Cloud
Leveraging massive amounts of compute resources to reduce time-to-market.
by Michael White
RISC-V Design Verification

Setting Up RISC-V Implementation Verification
How to set up and manage regressions in a lightweight verification tool.
by Shubhodeep Roy Choudhury
Sharpening Your Edge

Multitasking For Modern GPUs
GPUs are reaching beyond 3D graphics processing to power a range of new markets.
by Benny Har-Even
Design & Verification

SoC Co-Emulation Using Zynq Boards
Early and accurate hardware and software co-verification can eliminate severa...
February 27, 2020
by Michelle Mata
Against The Grain

Make-Or-Break Time For Portable Stimulus
We hear a lot from vendors about the new Portable Stimulus Standard, but how ...
October 25, 2018
by Neil Johnson

Knowledge Centers
Entities, people and technologies explored


  Trending Articles

3nm: Blurring Lines Between SoCs, PCBs And Packages

The end of Moore’s Law is providing options for shifting what goes where and how it gets designed.

by Ann Steffora Mutschler

The Challenges Of Building Inferencing Chips

As the field of AI continues to advance, different approaches to inferencing are being developed. Not all of them will work.

by Ann Steffora Mutschler

Improving EUV Process Efficiency

New materials and equipment could have a significant impact on both cost and speed.

by Mark LaPedus

Memory Issues For AI Edge Chips

In-memory computing becomes critical, but which memory and at what process node?

by Mark LaPedus

A New Breed Of Engineer

The industry needs a new breed of engineers that can understand both hardware and software and not just for firmware. Co-design has failed – we need co-engineers.

by Brian Bailey

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