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Systems & Design

Top Stories

Challenges For New AI Processor Architectures

Getting an AI seat in the data center is attracting a lot of investment, but there are huge headwinds.

Sweeping Changes Ahead For Systems Design

Demand for faster processing with increasingly diverse applications is prompting very different compute models.

Continuous Education For Engineers

Companies that invest in their employees' education often get rewarded with more productive and happier workers.

CEO Outlook: Chiplets, Longer IC Lifetimes, More End Markets

How the end of scaling and the electrification of everything are changing chip design.

Debug: The Schedule Killer

Time spent in debug is unpredictable. It consumes a large portion of the development cycle and can disrupt schedules, but good practices can minimi...

Rocky Road To Designing Chips In The Cloud

The EDA ecosystem is in the early stages of pivoting to the cloud, but not everything will move there.

Architectural Considerations For AI

What will it take to be successful with a custom chip for processing a neural network targeting the data center or the edge? A lot of money is look...

CEO Outlook: More Data, More Integration, Same Deadlines

How design is changing with the shift from homogeneous ICs to heterogeneous, multi-chip packages.

Continuing Challenges For Open-Source Verification

Is there an open-source business model that works for verification and debug?

Do We Have An IC Model Crisis?

Models enable automation and optimization, but today the need for new and more complex models is outstripping the ability to ratify and standardize...

More Top Stories »



Round Tables

CEO Outlook: More Data, More Integration, Same Deadlines

How design is changing with the shift from homogeneous ICs to heterogeneous, multi-chip packages.

Continuing Challenges For Open-Source Verification

Is there an open-source business model that works for verification and debug?

Standards, Open Source, and Tools

EDA has been more successful creating open languages and standards rather than promoting open-source collaboration. Will this change?

New Methodologies Create New Opportunities

Does RISC-V processor verification provide common ground to develop a new verification methodology, and will that naturally lead to new and potenti...

How Heterogeneous ICs Are Reshaping Design Teams

Increasingly complex systems are creating much different relationships between engineering specialities.

More Roundtables »



Multimedia

EDA In The Cloud

Is it technology or business models that are holding this back?

Next-Gen SerDes Roadmap

What’s new, what’s changed, and why.

Next-Gen Design Challenges

Converging workflows to deal with the intersection of rising system and scale complexity.

Better Quality RTL

How to boost efficiency in chip design.

High-Speed SerDes At 7/5nm

How to place macros inside a PHY in 7/5nm SoCs.

More Multimedia »



See All Posts in System-Level Design »

Latest Blogs

What Were They Thinking

Rethink, Not Replicate

COVID-19 caused many things to change, but only those that were rethought wil...
July 29, 2021
Frankly Speaking

Choosing The Right Model Fidelity For Your Digital Twin

Automatically developing the most appropriate model and its fidelity for a gi...
Lost Art Of Processor Verification

RISC-V Verification: The 5 Levels Of Simulation-Based Pro...

The design freedoms of RISC-V offer developers flexibility for innovation –...
A System Perspective

Robust Variation-Aware Smart Power Designs For Silicon Su...

Using machine learning to enable fast and accurate high-sigma analysis.
Looking Past The Horizon

Optimize Physical Verification Cost Of Ownership

Minimize unused compute resources during DRC and LVS runs.
Just A Formality

Formally Verifying SystemC/C++ Designs

As the level of abstraction increases, so too must the level of verification.
Embedded Customization

Is RISC-V The Future?

Barriers between processor types are breaking down and more complex, higher p...
Design & Verification

Developing A Real-Time SDR System

Implementing software-defined radio by integrating a tool like GNU Radio with...
Rule The Bugs

Invent A New Way To Do Your Job

While the fundamentals of good engineering remain the same, it's worth trying...
May 27, 2021
RISC-V Design Verification

An Insider’s View Of Verifying Custom RISC-V Proces...

How RISC-V verification ecosystems support flexibility in approaching a custo...
March 15, 2021
Editor's Note

The Next Wave Of Consolidation

Economic conditions are all there. So what's the holdup?
September 28, 2020

Knowledge Centers
Entities, people and technologies explored


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Piecing Together Chiplets

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