System-Level Design

Top Stories

Debug Tools Are Improving

Experts at the Table: How is machine learning going to impact debug, and what other improvements are on tap with debug?

Are Digital Twins Something For EDA To Pursue?

Part one: Defining the digital twins concept; the trouble with models; the issue with the ecosystem.

Hardware-Software Co-Design Reappears

There may be a second chance for co-design, but the same barriers also may get in the way.

Hybrid Emulation Takes Center Stage

Complex chips require a multitude of verification platforms working in sync, and that's where the challenges begin.

How To Optimize Verification

There's no such thing as a perfect strategy, but much can be improved.

Partitioning Drives Architectural Considerations

Experts at the Table, part 3: Systems of subsystems; heterogeneous systems; re-partitioning.

Breaking Down The Debug Process

Experts at the Table: Debug is not a monolithic task, and each stage in the processes needs a different focus.

HW/SW Design At The Intelligent Edge

Systems are extremely specific and power-constrained, which makes design extremely complex.

Open Source Processors: Fact Or Fiction?

Calling an open-source processor free isn't quite accurate.

Test Chips Play Larger Role At Advanced Nodes

Opinions diverge about whether to use fewer test chips, or whether to put more diagnostics into those chips.

More Top Stories »



Round Tables

Debug Tools Are Improving

Experts at the Table: How is machine learning going to impact debug, and what other improvements are on tap with debug?

Are Digital Twins Something For EDA To Pursue?

Part one: Defining the digital twins concept; the trouble with models; the issue with the ecosystem.

Partitioning Drives Architectural Considerations

Experts at the Table, part 3: Systems of subsystems; heterogeneous systems; re-partitioning.

Breaking Down The Debug Process

Experts at the Table: Debug is not a monolithic task, and each stage in the processes needs a different focus.

Evolution Of Verification Engineers

Experts at the Table, part 3: The role of a verification engineer will change and start to look a lot like knowledge management.

More Roundtables »



Multimedia

Signoff-Compatible CDC

Why netlist clock domain crossing is now an essential complement to RTL CDC at advanced nodes and in AI chips.

Verification In The Cloud

Why this shift is finally happening.

Analog Fault Simulation

How to improve coverage in safety-critical designs.

Verification At 7/5nm

What's missing for advanced-node SoCs and AI chips.

Safety-Critical Coverage

Verification in automotive, medical and industrial designs.

More Multimedia »



See All Posts in System-Level Design »

Latest Blogs

Just A Formality

A Holistic View Of RISC-V Verification

Successful projects entail more than core compliance to the ISA.
August 7, 2019
Editor's Note

China Accelerates Its Timetable

Government backing of homegrown tech stocks is the next phase of a much large...
July 25, 2019
What Were They Thinking

Semiconductor’s Dinosaurs

The dinosaur represents forced change and near extinction of what was once do...
Frankly Speaking

Verification Requirements For 5G To Enable A Perfect Stor...

From fixed wireless access to mission-critical devices, new 5G applications r...
Looking Past The Horizon

Which Glitch Is Which?

Analyze problems earlier with STA-based activity delay shifting and glitch po...
A System Perspective

Taking EDA To The Cloud

Get the most out of cloud computing resources by following a few guidelines.
Semi Thoughts

Memory IP: From Cobblestone To Cornerstone

Embedded memory started as a foundational element in chip design and has now ...
Programmed Complexity

Optimize MATLAB C/C++ Code For HLS

The design flow steps used to convert C/C++ algorithms to a hardware implemen...
Intelligent Analytics

DAC 2019 Was About More Than Just Chips

IoT security, artificial intelligence, and cloud EDA were all major themes th...
June 27, 2019
Design & Verification

Meanwhile, 35 Years Later…

Why SoC hybrid co-emulation for verification of hardware and software is so i...
Against The Grain

Make-Or-Break Time For Portable Stimulus

We hear a lot from vendors about the new Portable Stimulus Standard, but how ...
October 25, 2018

Knowledge Centers
Entities, people and technologies explored


  Trending Articles

Using Memory Differently To Boost Speed

Getting data in and out of memory faster is adding some unexpected challenges.

HBM2E: The E Stands for Evolutionary

The new version of the high bandwidth memory standard promises greater speeds and feeds and that’s about it.

Week In Review: Manufacturing, Test

Apple buys Intel’s phone modem biz; Optimal+ adds ML analytics; Q2 numbers; Japan-Korea trade war.

Cloudy Outlook Seen For IC Biz

The remainder of 2019 is mixed, but 2020 is looking better—at least for now.

Hardware-Software Co-Design Reappears

There may be a second chance for co-design, but the same barriers also may get in the way.