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Systems & Design

Top Stories

EDA Vendors Widen Use Of AI
Leveraging data across IC design flow improves time to market with more exploration of options and better optimization.
Published on September 29th,  2021 by Ed Sperling

Optimization Driving Changes In Microarchitectures
New approaches emerge as demand for improved power and performance overwhelm design tools.
Published on September 23rd,  2021 by Ann Steffora Mutschler

Containing The Explosion In Data
Designs are getting bigger, verification runs longer, and every stage of development and deployment provides valuable data — if you can find it.
Published on September 23rd,  2021 by Brian Bailey

Building Complex Chips That Last Longer
Experts at the Table: Using multiphysics and lots of computation to improve reliability and resiliency in advanced nodes and packages.
Published on September 23rd,  2021 by Ed Sperling

Analyzing Electro-Photonic Systems
Systems that contain both electrical and photonic components have to be designed as a single system, but modeling issues are slowing adoption.
Published on August 30th,  2021 by Brian Bailey

New Approaches For Processor Architectures
Flexibility and customization are now critical elements for optimizing performance and power.
Published on August 26th,  2021 by Ed Sperling

Modeling Chips From Atoms To Systems
The IC industry is struggling with blurring lines between different disciplines as chips are more tightly integrated with software in packages and ...
Published on August 26th,  2021 by Ann Steffora Mutschler

Steering The Semiconductor Industry
What does it take to get a new language, tool, or methodology established in the semiconductor industry? Disruption has rarely worked.
Published on August 26th,  2021 by Brian Bailey

Designing Chips In A ‘Lawless’ Industry
Mind-boggling number of options emerge, but which is best often isn't clear.
Published on August 2nd,  2021 by Ed Sperling

Challenges For New AI Processor Architectures
Getting an AI seat in the data center is attracting a lot of investment, but there are huge headwinds.
Published on July 29th,  2021 by Brian Bailey

More Top Stories »



Round Tables

Building Complex Chips That Last Longer
Experts at the Table: Using multiphysics and lots of computation to improve reliability and resiliency in advanced nodes and packages.
Published on September 23rd,  2021 by Ed Sperling

CEO Outlook: More Data, More Integration, Same Deadlines
How design is changing with the shift from homogeneous ICs to heterogeneous, multi-chip packages.
Published on June 24th,  2021 by Ed Sperling

Continuing Challenges For Open-Source Verification
Is there an open-source business model that works for verification and debug?
Published on June 1st,  2021 by Brian Bailey

Standards, Open Source, and Tools
EDA has been more successful creating open languages and standards rather than promoting open-source collaboration. Will this change?
Published on May 10th,  2021 by Brian Bailey

New Methodologies Create New Opportunities
Does RISC-V processor verification provide common ground to develop a new verification methodology, and will that naturally lead to new and potenti...
Published on April 27th,  2021 by Brian Bailey

More Roundtables »



Multimedia

Working With RISC-V
What's available, what's missing, what's next.
Published on August 17th,  2021 by Ed Sperling

EDA In The Cloud
Is it technology or business models that are holding this back?
Published on June 9th,  2021 by Ann Steffora Mutschler

Next-Gen SerDes Roadmap
What’s new, what’s changed, and why.
Published on May 25th,  2021 by Ed Sperling

Next-Gen Design Challenges
Converging workflows to deal with the intersection of rising system and scale complexity.
Published on April 20th,  2021 by Ed Sperling

Better Quality RTL
How to boost efficiency in chip design.
Published on February 2nd,  2021 by Ann Steffora Mutschler

More Multimedia »



See All Posts in System-Level Design »

Latest Blogs

Looking Past The Horizon

Using IP-XACT To Solve Design And Verification Problems
Using the IP integration standard to speed time to market and reduce costs.
October 13, 2021
by Anika Malhotra
What Were They Thinking

Wearables Disconnect
What can we expect to see come down the wearables runway, and what does it re...
September 23, 2021
by Brian Bailey
A System Perspective

Can We Efficiently Automate 2.5/3D IC ESD Protection Veri...
How to determine appropriate electrostatic discharge robustness requirements.
by Dina Medhat
Frankly Speaking

Microelectronics And The AI Revolution
Is there an industry domain leading the adoption of AI?
by Frank Schirrmeister
Embedded Customization

Why It’s The Perfect Time To Be Part Of The RISC-V ...
Industry momentum and interest in RISC-V continues to grow.
by Rupert Baines
DAC Exchange

58th DAC Online Program Is Now Live
Who's talking, and what they're talking about.
August 31, 2021
by Michelle Clancy
Just A Formality

Easing The Burden Of Early Bug Detection
Automated formal code inspection for early detection of implementation issues.
August 26, 2021
by Rob van Blommestein
Lost Art Of Processor Verification

RISC-V Verification: The 5 Levels Of Simulation-Based Pro...
The design freedoms of RISC-V offer developers flexibility for innovation –...
July 29, 2021
by Lee Moore
Design & Verification

Developing A Real-Time SDR System
Implementing software-defined radio by integrating a tool like GNU Radio with...
by Mariusz Grabowski
Rule The Bugs

Invent A New Way To Do Your Job
While the fundamentals of good engineering remain the same, it's worth trying...
May 27, 2021
by Hagai Arbel
RISC-V Design Verification

An Insider’s View Of Verifying Custom RISC-V Proces...
How RISC-V verification ecosystems support flexibility in approaching a custo...
March 15, 2021
by Shubhodeep Roy Choudhury

Knowledge Centers
Entities, people and technologies explored


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