Systems & Design

Top Stories

Problems And Solutions In Analog Design
At 7nm and beyond, and in many advanced packages, all devices are subject to noise and proximity effects.
Published on August 5th,  2020 by Ann Steffora Mutschler

Creating Better Models For Software And Hardware Verifica...
Experts at the Table: Rethinking approaches for more complex systems, ISAs, and chiplets.
Published on August 4th,  2020 by Ed Sperling

Universal Verification Methodology Running Out Of Steam
It’s time to move up in abstraction again as a complexity overwhelms a key approach.
Published on July 30th,  2020 by Ann Steffora Mutschler

Open-Source Verification
Sorting out what is meant by open-source verification is not easy, but it leaves the door open to new approaches
Published on July 30th,  2020 by Brian Bailey

RISC-V Gaining Traction
Experts at the Table: Extensible instruction-set architecture is drawing attention from across the industry and supply chain.
Published on July 30th,  2020 by Ed Sperling

Challenges For A Post-Moore’s Law World
More customization and a different message for the chip industry.
Published on July 27th,  2020 by Ed Sperling

EDA On Board With New Package Options
But with so many variations in multi-chip packages, there isn’t a single design flow.
Published on July 22nd,  2020 by Ann Steffora Mutschler

Chip Reliability Vs. Cost
CEO Outlook: Market shifts, higher productivity per engineer and the overhead and opportunities for security and reliability.
Published on July 5th,  2020 by Ed Sperling

Gaps Emerging In System Integration
Integration used to be a functionality problem, but global issues such as power are changing that.
Published on June 29th,  2020 by Brian Bailey

Open-Source Hardware Momentum Builds
RISC-V drives new attention to this market, but the cost/benefit equation is different for open-source hardware than software.
Published on June 25th,  2020 by Brian Bailey

More Top Stories »



Round Tables

Creating Better Models For Software And Hardware Verifica...
Experts at the Table: Rethinking approaches for more complex systems, ISAs, and chiplets.
Published on August 4th,  2020 by Ed Sperling

RISC-V Gaining Traction
Experts at the Table: Extensible instruction-set architecture is drawing attention from across the industry and supply chain.
Published on July 30th,  2020 by Ed Sperling

Chip Reliability Vs. Cost
CEO Outlook: Market shifts, higher productivity per engineer and the overhead and opportunities for security and reliability.
Published on July 5th,  2020 by Ed Sperling

Simplifying And Speeding Up Verification
Experts at the Table: The impact of AI, chiplets, and more precise interconnects.
Published on June 16th,  2020 by Ed Sperling

What Will The Next-Gen Verification Flow Look Like?
Experts at the Table: Machine learning is an essential element for dealing with complexity and shorter design cycles, but it may require a differen...
Published on May 28th,  2020 by Ed Sperling

More Roundtables »



Multimedia

High-Speed SerDes At 7/5nm
How to place macros inside a PHY in 7/5nm SoCs.
Published on June 2nd,  2020 by Ed Sperling

Rising Packaging Complexity
Why advanced packaging is still so difficult.
Published on May 19th,  2020 by Ed Sperling

Speeding Up Verification Using SystemC
How HLS plus formal can significantly reduce optimization and debug time.
Published on March 23rd,  2020 by Ed Sperling

Timing Closure At 7/5nm
Why shifting left in a complex design is critical.
Published on March 17th,  2020 by Ed Sperling

Banking On FPGA Prototyping
Where the biggest savings are in ASIC design.
Published on March 4th,  2020 by Ed Sperling

More Multimedia »



See All Posts in System-Level Design »

Latest Blogs

Editor's Note

Rethinking Competitive One Upmanship Among Foundries
Just because features are smaller doesn't make them more attractive.
August 3, 2020
by Ed Sperling
Looking Past The Horizon

EDA Forms The Basis For Designing Secure Systems
How to accelerate the design process at a lower cost and with less risk.
by Adam Cron
What Were They Thinking

Engineering Within Constraints
Science and engineering form a partnership. They rely on each other and have ...
July 30, 2020
by Brian Bailey
Frankly Speaking

Computational Software: The Foundation Across Software Di...
Hyperscale computing and a focus on the interaction between domains are pushi...
by Frank Schirrmeister
Design & Verification

Linting RISC-V Designs
How to validate design code robustness without running simulations.
by Alex Gnusin
Just A Formality

IP Integration Verification At DVClub Europe
The online, free event will explore solutions to the challenge of integrating...
by Saša Stamenković
A System Perspective

Running With O-RAN
Ensuring pre- and post-silicon verification complies with developing 5G stand...
by Mika Castren
Sharpening Your Edge

Smarter, Safer Surround-View For Cars
Making an automotive safety assistance feature more realistic and informative.
by Mike Barnes
Rule The Bugs

Methodology Vs. Problem-Solving
Should you follow a proven verification path or blaze your own?
July 22, 2020
by Hagai Arbel
DAC Exchange

Designer And IP Tracks Swell With Focus On ML, Security A...
Submitted papers show what's important to engineers as design flows increase ...
July 13, 2020
by Michelle Clancy
Embedded Customization

About The SweRV Core EH2
Checking out a new dual threaded commercial RISC-V core for IoT, artificial i...
June 25, 2020
by Roddy Urquhart

Knowledge Centers
Entities, people and technologies explored


  Trending Articles

Manufacturing Bits: July 21

Intel’s next-gen MRAM; silicon oxide ReRAM; FeFETs.

by Mark LaPedus

RISC-V Gaining Traction

Experts at the Table: Extensible instruction-set architecture is drawing attention from across the industry and supply chain.

by Ed Sperling

Universal Verification Methodology Running Out Of Steam

It’s time to move up in abstraction again as a complexity overwhelms a key approach.

by Ann Steffora Mutschler

The Race To Much More Advanced Packaging

Hybrid bonding opens up a big improvement in die-to-die performance, but getting there is not trivial.

by Mark LaPedus

Speeding Up The R&D Metrology Process

The goal is to use fab-like methods in the lab, but that’s not easy.

by Mark LaPedus

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