Systems & Design

Top Stories

Problems And Solutions In Analog Design

At 7nm and beyond, and in many advanced packages, all devices are subject to noise and proximity effects.

Creating Better Models For Software And Hardware Verifica...

Experts at the Table: Rethinking approaches for more complex systems, ISAs, and chiplets.

Universal Verification Methodology Running Out Of Steam

It’s time to move up in abstraction again as a complexity overwhelms a key approach.

Open-Source Verification

Sorting out what is meant by open-source verification is not easy, but it leaves the door open to new approaches

RISC-V Gaining Traction

Experts at the Table: Extensible instruction-set architecture is drawing attention from across the industry and supply chain.

Challenges For A Post-Moore’s Law World

More customization and a different message for the chip industry.

EDA On Board With New Package Options

But with so many variations in multi-chip packages, there isn’t a single design flow.

Chip Reliability Vs. Cost

CEO Outlook: Market shifts, higher productivity per engineer and the overhead and opportunities for security and reliability.

Gaps Emerging In System Integration

Integration used to be a functionality problem, but global issues such as power are changing that.

Open-Source Hardware Momentum Builds

RISC-V drives new attention to this market, but the cost/benefit equation is different for open-source hardware than software.

More Top Stories »



Round Tables

Creating Better Models For Software And Hardware Verifica...

Experts at the Table: Rethinking approaches for more complex systems, ISAs, and chiplets.

RISC-V Gaining Traction

Experts at the Table: Extensible instruction-set architecture is drawing attention from across the industry and supply chain.

Chip Reliability Vs. Cost

CEO Outlook: Market shifts, higher productivity per engineer and the overhead and opportunities for security and reliability.

Simplifying And Speeding Up Verification

Experts at the Table: The impact of AI, chiplets, and more precise interconnects.

What Will The Next-Gen Verification Flow Look Like?

Experts at the Table: Machine learning is an essential element for dealing with complexity and shorter design cycles, but it may require a differen...

More Roundtables »



Multimedia

High-Speed SerDes At 7/5nm

How to place macros inside a PHY in 7/5nm SoCs.

Rising Packaging Complexity

Why advanced packaging is still so difficult.

Speeding Up Verification Using SystemC

How HLS plus formal can significantly reduce optimization and debug time.

Timing Closure At 7/5nm

Why shifting left in a complex design is critical.

Banking On FPGA Prototyping

Where the biggest savings are in ASIC design.

More Multimedia »



See All Posts in System-Level Design »

Latest Blogs

Editor's Note

Rethinking Competitive One Upmanship Among Foundries

Just because features are smaller doesn't make them more attractive.
August 3, 2020
Looking Past The Horizon

EDA Forms The Basis For Designing Secure Systems

How to accelerate the design process at a lower cost and with less risk.
What Were They Thinking

Engineering Within Constraints

Science and engineering form a partnership. They rely on each other and have ...
July 30, 2020
Frankly Speaking

Computational Software: The Foundation Across Software Di...

Hyperscale computing and a focus on the interaction between domains are pushi...
Design & Verification

Linting RISC-V Designs

How to validate design code robustness without running simulations.
Just A Formality

IP Integration Verification At DVClub Europe

The online, free event will explore solutions to the challenge of integrating...
A System Perspective

Running With O-RAN

Ensuring pre- and post-silicon verification complies with developing 5G stand...
Sharpening Your Edge

Smarter, Safer Surround-View For Cars

Making an automotive safety assistance feature more realistic and informative.
Rule The Bugs

Methodology Vs. Problem-Solving

Should you follow a proven verification path or blaze your own?
July 22, 2020
DAC Exchange

Designer And IP Tracks Swell With Focus On ML, Security A...

Submitted papers show what's important to engineers as design flows increase ...
July 13, 2020
Embedded Customization

About The SweRV Core EH2

Checking out a new dual threaded commercial RISC-V core for IoT, artificial i...
June 25, 2020

Knowledge Centers
Entities, people and technologies explored


  Trending Articles

Manufacturing Bits: July 21

Intel’s next-gen MRAM; silicon oxide ReRAM; FeFETs.

RISC-V Gaining Traction

Experts at the Table: Extensible instruction-set architecture is drawing attention from across the industry and supply chain.

Universal Verification Methodology Running Out Of Steam

It’s time to move up in abstraction again as a complexity overwhelms a key approach.

The Race To Much More Advanced Packaging

Hybrid bonding opens up a big improvement in die-to-die performance, but getting there is not trivial.

Speeding Up The R&D Metrology Process

The goal is to use fab-like methods in the lab, but that’s not easy.