Systems & Design

Top Stories

Swapping Out Chiplets: I/Os Vs. Compute
Multi-die assemblies give chip architects the option to change some dies while keeping the rest of the system intact, but which is best to keep?
Published on May 28th, 2026 by Liz Allan

Observability Is Essential For Modern Silicon
What on-die visibility reveals, and why it's especially important for AI, automotive, aerospace, and advanced packaging.
Published on May 28th, 2026 by Ann Mutschler

Options Grow For Standardizing Data Movement And Sharing ...
But figuring out which ones to use, and when to use them, isn't always clear.
Published on May 20th, 2026 by Ed Sperling

Confusion Grows With More Interconnect Options And Tradeoffs
Each standard serves a specific use case, so chip architects are choosing more than one for a single design.
Published on May 18th, 2026 by Liz Allan

Using AI To Monitor Dashboards In Chips And Systems
AI agents can be used to identify potential issues during operation and react before it's too late.
Published on May 6th, 2026 by Ed Sperling

Designing Chips In The Context Of Rapidly Evolving AI
Long‑running agents, tool-calling LLMs, and multimodal chaos are rewriting edge compute rules, and making chip design more challenging.
Published on May 4th, 2026 by Ann Mutschler

Creating Agentic EDA Methodologies
Current approaches involve multiple tools, vendors, designs, data formats, and abstractions. Can agents really use them all?
Published on April 30th, 2026 by Brian Bailey

NoC Coherency Challenges Balloon With AI SoCs And Chiplets
Complex chips need coherent and non-coherent sub-NoCs to ensure efficient data paths. Correct hierarchy is essential.
Published on April 30th, 2026 by Liz Allan

AI Growing Impact On Chip Design And EDA Tools
Demand for faster design and more automation grows from key customers.
Published on April 15th, 2026 by Ed Sperling

Startup Funding: Q1 2026
Massive rounds for AI, EDA, and manufacturing; 80 startups raise $8.4B.
Published on April 13th, 2026 by Jesse Allen

More Top Stories »



Round Tables

Observability Is Essential For Modern Silicon
What on-die visibility reveals, and why it's especially important for AI, automotive, aerospace, and advanced packaging.
Published on May 28th, 2026 by Ann Mutschler

Designing Chips In The Context Of Rapidly Evolving AI
Long‑running agents, tool-calling LLMs, and multimodal chaos are rewriting edge compute rules, and making chip design more challenging.
Published on May 4th, 2026 by Ann Mutschler

AI Growing Impact On Chip Design And EDA Tools
Demand for faster design and more automation grows from key customers.
Published on April 15th, 2026 by Ed Sperling

AI’s Potential And Limitations In Chip Design
Full automation is still a goal, but humans will still be in the loop for the foreseeable future.
Published on April 1st, 2026 by Ed Sperling

Verifying Scale-Up And Scale-Out In Data Centers
Navigating a sea of standards and options in a rack and between racks.
Published on February 26th, 2026 by Ed Sperling

More Roundtables »



Multimedia

Building Multi-Agent Systems For ASIC Flows
How agents can be used to divide and conquer IC design problems.
Published on June 10th, 2026 by Ed Sperling

The Evolution Of UCIe
How the standard matured from simple connectivity to secure data movement across multiple chiplets and packaging approaches.
Published on June 2nd, 2026 by Ed Sperling

Overcoming Bottlenecks In Data Movement
Where the choke points are in AI systems and what to do about them.
Published on May 27th, 2026 by Ed Sperling

Why Proof Convergence Matters
Leveraging patterns in formal verification to reach sign-off faster.
Published on April 20th, 2026 by Ed Sperling

How AI Will Automate Chip Design
Step-by-step application of AI in EDA.
Published on March 17th, 2026 by Ed Sperling

More Multimedia »



See All Posts in System-Level Design »

Latest Blogs

Making Formal Normal

Why Your NoC Verification Strategy Must Consider Using Fo...
Exhaustive proofs are the only way to find deep corner-case bugs that can res...
May 28, 2026
by Ashish Darbari
A System Perspective

Automating Traditional PCB Layout Verification With Elect...
Going beyond traditional spacing and distance checks to incorporate signal in...
May 28, 2026
by Rory Riggs
NoC NoC

Using SystemC TLM Modeling To Solve AI Data Movement Chal...
Understanding whether the interconnect can support the workload before the de...
May 28, 2026
by Andy Nightingale
From Simulation To Always-On Physics

Foundation Model For Physics: The Next Layer Of Intellige...
Making validated physics reasoning continuously available across the engineer...
May 28, 2026
by John Bruggeman
Looking Past The Horizon

Faster Verification Debug With AI
Automate a wide range of tasks, including waveform inspection, logfile analys...
May 28, 2026
by Taruna Reddy
The Next Thread

Wafer-Scale vs. Chiplets: The New War? Part 1
The chip that broke all the rules.
May 28, 2026
by Nandan Nayampally
First By Design

The Shape Of Prompts: Exploring Their Effect On Inference...
Aligning GPU, memory, storage, and network resources in a balanced and effici...
May 28, 2026
by Amritam Putatunda
Clock Talk

A Bench-To-In-Field Telemetry Platform For Data Center Po...
Enabling SoCs to run at their true power and performance limits across the fu...
May 28, 2026
by Aakash Jani
Intelligent System Design

A Scalable Answer To Advanced-Node Characterization
The growing pain no library team can ignore.
May 28, 2026
by Rajshekharayya Hiremath
AI Agents In Design And Verification

Autonomous ASIC Root Cause Analysis
An agentic AI-based approach to end-to-end bug resolution using both error lo...
December 23, 2025
by Mehir Arora

Knowledge Centers
Entities, people and technologies explored


  Trending Articles

The Sub-2nm Paradox
Reducing variation in manufacturing, monitoring behavior over time, and targeting specific workloads can have a big impact on power, performance, and area/cost.
by Ed Sperling

Chip Industry Week In Review
Taiwan, Europe packaging buildout; 2nm ramps; quantum big $; 2 new university hubs; agent honeypots; Samsung strike averted; extreme environment chip design; quantum-dot qubit device fabricated w/high-NA EUV; EU flagship power electronics project; CNTs.
by The SE Staff

Chip Industry Week In Review
AI panel-level packaging innovations at ECTC; cool HBM; 2nm EDA tools; side-channel attacks in 2.5/3D; Huawei claims; IC talent initiative; glass core substrates; memory test facility; Taiwan investments; SiC teamup; DRAM sizing; sequentially stacking silicon; MIPI A-PHY SerDes automotive compliance.
by The SE Staff

With Chiplets, What Role Does Economics Play?
Costs can rise with chiplets. Will that change? Will it matter?
by Bryon Moyer

Confusion Grows With More Interconnect Options And Tradeoffs
Each standard serves a specific use case, so chip architects are choosing more than one for a single design.
by Liz Allan

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy