System-Level Design

Top Stories

Training Tomorrow’s Chip Designers

The semiconductor industry partners with academia in a variety of ways to support the next generation of electrical engineers.

CEO Outlook: It Gets Much Harder From Here

Experts at the Table, Part 1: As power/performance benefits shrink at each new node, engineers are turning to different chip architectures and new ...

How To Integrate An Embedded FPGA

Adding an eFPGA into an SoC is more complex than just adding an accelerator.

Why IP Quality Is So Difficult To Determine

How it is characterized, verified and used can have a big impact on reliability and compatibility in a design.

Adding Order And Structure To Verification

How industry experts reacted to their first encounter with a formal capability maturity model.

Evolution Of Verification Engineers

Experts at the Table, part 3: The role of a verification engineer will change and start to look a lot like knowledge management.

IP Requires System Context At 6/5/3nm

At each new process node, gates are free. That opens the door to a lot more IP blocks, and a lot of new challenges.

Automotive, AI Drive Big Changes In Test

DFT strategies are becoming intertwined with design strategies at the beginning of the design process.

When Verification Leads

Experts at the Table, part 1: Would an executable requirements document transform verification or design? Experts have differing ideas.

The Case For Embedded FPGAs Strengthens And Widens

Combining the flexibility of a FPGA with the performance and cost benefits of an SoC is pushing this technology well into the mainstream.

More Top Stories »



Round Tables

Evolution Of Verification Engineers

Experts at the Table, part 3: The role of a verification engineer will change and start to look a lot like knowledge management.

Incremental System Verification

Experts at the table: Part 2. How does a PSS model get verified and who will create that model? What happens when models extend beyond the specific...

When Verification Leads

Experts at the Table, part 1: Would an executable requirements document transform verification or design? Experts have differing ideas.

The Role Of EDA In AI

Experts at the Table, part 3: Which aspects of AI implementation should EDA create tools for?

From AI Algorithm To Implementation

Experts at the Table, part 2: The transformation from algorithm to implementation has some significant problems that are not being properly address...

More Roundtables »



Multimedia

Analog Fault Simulation

How to improve coverage in safety-critical designs.

Verification At 7/5nm

What's missing for advanced-node SoCs and AI chips.

Safety-Critical Coverage

Verification in automotive, medical and industrial designs.

Billion-Gate Design Connectivity

Dealing with integration issues in large, complex chips.

Debug Changes At Advanced Nodes

Why traditional verification methods are becoming less effective.

More Multimedia »



See All Posts in System-Level Design »

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