Observability Is A Missing Layer In AI-Era Chiplet Design
In next-generation silicon, AI can interpret system behavior at scale, but only if observability is designed into the fabric as a first-class archi...
I/O Design Challenges Grow In AI Data Centers And HPC Clu...
Physical I/Os can be a chokepoint for high-performance chips and high-speed interconnect protocols, requiring design tradeoffs and extra reliabilit...
Verification Methodologies Struggle To Keep Up With AI
Engineers are flooded with new capabilities. The problem now is how best to deploy them.
Executive Outlook: Agentic AI’s Impact On Chip Design
Can engineers trust AI to get everything right in semiconductor design and verification?
Designing Chips That Can Explain Themselves
On-die monitors, localized analytics, and lifecycle data are giving architects new ways to close the gap between design intent and silicon behavior.
Swapping Out Chiplets: I/Os Vs. Compute
Multi-die assemblies give chip architects the option to change some dies while keeping the rest of the system intact, but which is best to keep?
Toward Agentic Verification
Using AI agents for verifying designs holds huge potential, but can it deliver? And what comes next?
Observability Is Essential For Modern Silicon
What on-die visibility reveals, and why it's especially important for AI, automotive, aerospace, and advanced packaging.
Options Grow For Standardizing Data Movement And Sharing ...
But figuring out which ones to use, and when to use them, isn't always clear.
Confusion Grows With More Interconnect Options And Tradeoffs
Each standard serves a specific use case, so chip architects are choosing more than one for a single design.
More Top Stories »
Observability Is A Missing Layer In AI-Era Chiplet Design
In next-generation silicon, AI can interpret system behavior at scale, but only if observability is designed into the fabric as a first-class archi...
Executive Outlook: Agentic AI’s Impact On Chip Design
Can engineers trust AI to get everything right in semiconductor design and verification?
Designing Chips That Can Explain Themselves
On-die monitors, localized analytics, and lifecycle data are giving architects new ways to close the gap between design intent and silicon behavior.
Observability Is Essential For Modern Silicon
What on-die visibility reveals, and why it's especially important for AI, automotive, aerospace, and advanced packaging.
Designing Chips In The Context Of Rapidly Evolving AI
Long‑running agents, tool-calling LLMs, and multimodal chaos are rewriting edge compute rules, and making chip design more challenging.
More Roundtables »
How Far Left Can You Shift?
Complex chips require much more work earlier in the flow.
Signoff Of Synthesis-Optimized Registers
When is a complex chip design ready to be shipped to manufacturing?
Building Multi-Agent Systems For ASIC Flows
How agents can be used to divide and conquer IC design problems.
The Evolution Of UCIe
How the standard matured from simple connectivity to secure data movement across multiple chiplets and packaging approaches.
Overcoming Bottlenecks In Data Movement
Where the choke points are in AI systems and what to do about them.
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