System-Level Design

Top Stories

Whatever Happened to High-Level Synthesis?

Experts at the table, part 2: Playing in an IP integration world, defining verification flows and compatibility with a virtual prototype.

What’s Next In Neural Networking?

Technology begins to twist in different directions and for different markets.

Can Formal Replace Simulation?

Exclusive: Formal leaders discuss the ways in which they are stretching formal tools to the limit to solve an ever-increasing array of tasks.

Speeding Up Neural Networks

Adding more dimensions creates more data, all of which needs to be processed using new architectural approaches.

Design Complexity Drives New Automation

It now takes an entire ecosystem to build a chip—and lots of expensive tools.

Supporting CPUs Plus FPGAs

Experts at the table, part 3: Partitioning, security issues, verification and field upgradeability.

Custom Chip Verification Issues Grow

No simple solutions to deal with market-specific requirements and advanced process node issues.

EDA Revenue Up 18.9%

PCB and IP buoyed the healthy results for Q4.

Challenges Grow For IP Reuse

Methodologies for integration become a competitive tool as complexity and possible options skyrocket.

Users Talk Back On Standards Process

How does a standard get created? A lot of hard work and balancing different opinions can be frustrating, but that communication is vital.

More Top Stories »



Round Tables

Whatever Happened to High-Level Synthesis?

Experts at the table, part 2: Playing in an IP integration world, defining verification flows and compatibility with a virtual prototype.

Whatever Happened To High-Level Synthesis?

Experts at the table, part 1: What progress has been made in High Level Synthesis and what can we expect in the near future?

Supporting CPUs Plus FPGAs

Experts at the table, part 3: Partitioning, security issues, verification and field upgradeability.

Supporting CPUs Plus FPGAs

Experts at the table, part 2: Who is the real user and how will they program this type of solution?

Supporting CPUs Plus FPGAs

Experts at the table, part 1: What the toolchain looks like today and the different mindsets within those flows.

More Roundtables »



Multimedia

Biz Talk: ASICs

eSilicon's CEO discusses the future of scaling, the rollout of advanced packaging, and where the next big opportunities will be.

Tech Talk: Timing Closure

Why timing closure is suddenly a problem again and what to do about it.

Tech Talk: Earlier Software

How to knock a year off software development.

Tech Talk: ADAS

Why the Advanced Driver Assistance Systems standard is so important and where the potential pitfalls are.

Tech Talk: 2.5D Issues

How ready is this packaging approach and what problems remain?

More Multimedia »



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