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Systems & Design

Top Stories

How Heterogeneous ICs Are Reshaping Design Teams

Increasingly complex systems are creating much different relationships between engineering specialities.

Computing Where Data Resides

Computational storage approaches push power and latency tradeoffs.

Verification In The Open Source Era

What does open-source verification mean in the context of a RISC-V processor core? Does it provide free tools, free testbenches, or the freedom to ...

Waiting For Chiplet Standards

An ecosystem is required to make chiplets a viable strategy for long-term success, and ecosystems are built around standards. Those standards are b...

Demand for IC Resilience Drives Methodology Changes

New ways of connecting design, verification, test, and in-field data are needed for longer lifetimes and more critical applications.

Design Issues For Chips Over Longer Lifetimes

Experts at the Table: Keeping systems running for decades can cause issues ranging from compatibility and completeness of updates to unexpected sec...

Chiplets For The Masses

Chiplets are technically and commercially viable, but not yet accessible to the majority of the market. How does the ecosystem get established?

Firmware Skills Shortage

Adding intelligence into devices requires a different skill set, and finding enough qualified people is becoming a challenge — especially in less...

When Is Verification Done?

The actual time may be more of a fuzzy risk assessment than a clear demarcation.

Big Challenges In Verifying Cyber-Physical Systems

Experts at the Table: Models and standards are rare and insufficient, making it difficult to account for hardware-software and system-level interac...

More Top Stories »



Round Tables

How Heterogeneous ICs Are Reshaping Design Teams

Increasingly complex systems are creating much different relationships between engineering specialities.

Verification In The Open Source Era

What does open-source verification mean in the context of a RISC-V processor core? Does it provide free tools, free testbenches, or the freedom to ...

Design Issues For Chips Over Longer Lifetimes

Experts at the Table: Keeping systems running for decades can cause issues ranging from compatibility and completeness of updates to unexpected sec...

Big Challenges In Verifying Cyber-Physical Systems

Experts at the Table: Models and standards are rare and insufficient, making it difficult to account for hardware-software and system-level interac...

RISC-V: Will There Be Other Open-Source Cores?

Experts at the Table: The current state of open-source tools, and what the RISC-V landscape will look like by 2025.

More Roundtables »



Multimedia

Better Quality RTL

How to boost efficiency in chip design.

High-Speed SerDes At 7/5nm

How to place macros inside a PHY in 7/5nm SoCs.

Rising Packaging Complexity

Why advanced packaging is still so difficult.

Speeding Up Verification Using SystemC

How HLS plus formal can significantly reduce optimization and debug time.

Timing Closure At 7/5nm

Why shifting left in a complex design is critical.

More Multimedia »



See All Posts in System-Level Design »

Latest Blogs

Looking Past The Horizon

Requirements For Exhaustive SoC Reset Domain Crossing Checks

As the number of reset domains rises, thorough pre-silicon verification is es...
April 13, 2021
Just A Formality

Unlock Your Vision… And A Bit Of EDA History

Fifth annual puzzle contest challenged engineers to reveal design secrets hid...
March 29, 2021
Embedded Customization

What Does RISC-V Stand For?

A brief history of the open ISA.
What Were They Thinking

Stuck In A Rut

Has EDA failed to innovate, or has the semiconductor industry shown an unwill...
March 25, 2021
Frankly Speaking

Digital Transformation In Aerospace And Defense Applications

A look at how defense contractors and the US Air Force are increasing verific...
A System Perspective

Aging Analysis Common Model Interface Gains Momentum

Enabling a standard, simulator agnostic interface for aging modeling, simulat...
Design & Verification

Processing With FPGAs On Mars

Why FPGAs were used in the Perseverance rover for applications such as radar ...
RISC-V Design Verification

An Insider’s View Of Verifying Custom RISC-V Proces...

How RISC-V verification ecosystems support flexibility in approaching a custo...
March 15, 2021
Rule The Bugs

Bug Escapes And The Definition Of Done

What needs to change in verification to improve the rate of first silicon suc...
January 28, 2021
Lost Art Of Processor Verification

The Lost Art Of Processor Verification

Using SoC methodologies for RISC-V processor DV.
January 4, 2021
Editor's Note

The Next Wave Of Consolidation

Economic conditions are all there. So what's the holdup?
September 28, 2020

Knowledge Centers
Entities, people and technologies explored


  Trending Articles

The Future Of Transistors And IC Architectures

The more compute power, the better. But what’s the best way to get there?

EUV Pellicles Finally Ready

Yield rises with mask protection; multiple sources will likely reduce costs.

What Goes Wrong In Advanced Packages

More heterogeneous designs and packaging options add challenges across the supply chain, from design to manufacturing and into the field.

Chasing After Carbon Nanotube FETs

CNTs promise big performance improvements, but achieving consistency and replacing incumbent technologies will be difficult.

Waiting For Chiplet Standards

An ecosystem is required to make chiplets a viable strategy for long-term success, and ecosystems are built around standards. Those standards are beginning to emerge today.