First By Design
Democratizing Design: How The CHIPS Act Is Reshaping EDA ...
Reflections from a recent panel discussion at DAC, The Chips to Systems Confe...
July 2, 2025
A System Perspective
Rethinking Chip Debug
Complexity demands a smarter solution.
June 30, 2025
Intelligent System Design
Redefining SoC Design: The Shift To Secure Chiplet-Based ...
Ensuring trusted execution across multiple chiplets and vendors is more compl...
June 26, 2025
The Next Wave
Programmable Hardware Delivers 10,000X Improvement In Ver...
How FPGAs can be used to identify bursts of errors in wireline networking and...
June 26, 2025
Looking Past The Horizon
Closing The RISC-V Verification Disconnect
Plan for multiple complementary verification methodologies for different leve...
May 29, 2025
NoC NoC
CSR Management: Life Beyond Spreadsheets
Eliminating hardware-software mismatches and ensuing design re-spins with an ...
May 29, 2025
Making Formal Normal
How To Optimize Silicon Utilization To Improve PPA
As designs grow more complex, detecting and eliminating underutilized compone...
April 29, 2025
Memory/IO Wall Solutions
AI Infrastructure At A Crossroads
Weighing efficiency gains vs. the scale of personalization.
January 30, 2025
The Chiplet Connection
Enabling Innovative Multi-Vendor Chiplet-Based Designs
What makes chiplets so attractive, and why they are essential for future desi...
September 26, 2024
Clock Talk
Droop And Silent Data Corruption
Advanced silicon lifecycle analytics and on-die telemetry are needed to count...
July 25, 2024
Power Delivery Challenges For AI Chips
Rising power densities and new architectures are forcing a rethinking of interconnects, materials, and thermal management.
Novel Assembly Approaches For 3D Device Stacks
ECTC progress report on enabling technologies, including cooling chiplets, 1µm hybrid bonding, RDL buildups, and co-packaged optics.
Startup Funding: Q2 2025
New architectures and manufacturing methods draw investors; 75 startups raise $1.9 billion.
Chip Industry Week in Review
$60B fab buildout; Chinese automakers tout 100% homemade chips; 2nm custom SRAM; Cadence's virtual platform buy; multi-chiplet NoC; HBM roadmap; MIT's GaN fab technique; 30% tax credit; Taiwan export restrictions, power vulnerability; global memory market; rad-tolerant memory; 2D, non-silicon computer.
EDA’s Top Execs Map Out An AI-Driven Future
AI is accelerating the need for 3D-ICs and digital twins, and causing lots of disruption along the way.