System-Level Design

Top Stories

Using FPGAs For AI
How good are standard FPGAs for AI purposes, and how different will dedicated FPGA-based devices be from them?
Published on December 2nd,  2019 by Brian Bailey

Transforming Silicon Bring-Up
The role of silicon for verification and validation is changing. While there is the desire to Shift Left, silicon also has become a valuable verifi...
Published on November 26th,  2019 by Brian Bailey

Thoroughly Verifying Complex SoCs
With so many variables, verifying complex, heterogenous designs is a task with many tentacles.
Published on November 26th,  2019 by Ann Steffora Mutschler

Optimizing Hardware Faster
Silexica's CEO talks about why high-level synthesis has become so important across different markets.
Published on November 26th,  2019 by Ed Sperling

Portable Stimulus And Digital Twins
Experts at the Table: How Portable Stimulus plays with the digital twin and the drive toward system-level coverage.
Published on November 25th,  2019 by Brian Bailey

RISC-V Markets, Security And Growth Prospects
Experts at the Table: Why RISC-V has garnered so much attention, what still needs to be done, and where it will likely find its greatest success.
Published on November 18th,  2019 by Ed Sperling

Service Revenue Growing With Chip Complexity
Demand for outside expertise grows with new markets and architectures.
Published on November 4th,  2019 by Ann Steffora Mutschler

Migrating 3D Into The Mainstream
Experts at the Table: The creation of complex, packaged systems affects everything in the design flow and requires a systems approach.
Published on October 31st,  2019 by Brian Bailey

Rapid Evolution For Verification Plans
While many companies do have verification plans, demands on those plans are changing faster than most companies can evolve.
Published on October 28th,  2019 by Brian Bailey

Utilizing Computational Memory
How processing near memory could change the compute landscape.
Published on October 24th,  2019 by Brian Bailey

More Top Stories »



Round Tables

Portable Stimulus And Digital Twins
Experts at the Table: How Portable Stimulus plays with the digital twin and the drive toward system-level coverage.
Published on November 25th,  2019 by Brian Bailey

RISC-V Markets, Security And Growth Prospects
Experts at the Table: Why RISC-V has garnered so much attention, what still needs to be done, and where it will likely find its greatest success.
Published on November 18th,  2019 by Ed Sperling

Migrating 3D Into The Mainstream
Experts at the Table: The creation of complex, packaged systems affects everything in the design flow and requires a systems approach.
Published on October 31st,  2019 by Brian Bailey

RISC-V Challenges And Opportunities
Who makes money with an open-source ISA, the current state of the RISC-V ecosystem, and what differentiates one vendor from the next.
Published on October 24th,  2019 by Ed Sperling

Extending Portable Stimulus
Experts at the Table: With the initial standard in place, what can we expect in terms of broadening its scope to other domains and applications?
Published on October 16th,  2019 by Brian Bailey

More Roundtables »



Multimedia

Distributed Design Implementation
Simplifying timing closure and sign-off in complex heterogeneous designs.
Published on December 4th,  2019 by Ed Sperling

Finding Hardware Trojans
Why locating security threats in hardware is so difficult.
Published on December 3rd,  2019 by Ed Sperling

Which Verification Engine When
How complexity and more data are affecting the design flow.
Published on October 31st,  2019 by Ed Sperling

Visually Assisted Layout In Custom Design
A faster way to optimize designs and find errors.
Published on October 29th,  2019 by Ed Sperling

Signoff-Compatible CDC
Why netlist clock domain crossing is now an essential complement to RTL CDC at advanced nodes and in AI chips.
Published on July 29th,  2019 by Ed Sperling

More Multimedia »



See All Posts in System-Level Design »

Latest Blogs

Just A Formality

OneSpin Users Gather in Munich
Successful event offers opportunity to share tips and technology.
December 2, 2019
by Rob van Blommestein
Editor's Note

Designing In 4D
Why time is becoming an essential element, and what it means for chip archite...
November 26, 2019
by Ed Sperling
What Were They Thinking

Better, Not Best
There is little point creating the best possible device when slightly better ...
by Brian Bailey
Looking Past The Horizon

Static Verification Of Low Power Designs
The stages of a modern low power development and verification flow.
by Himanshu Bhatt
Frankly Speaking

Verification In The Era Of Autonomous Driving, Artificial...
The importance of data is changing traditional value creation in electronics ...
by Frank Schirrmeister
Design & Verification

Developing Robust Finite State Machines Code With Lint Tools
Revealing finite state machine design bugs at the earliest stages of code dev...
by Alex Gnusin
A System Perspective

A Reliable I/O Ring For A Reliable SoC
Integrate disparate I/O ring rules from various IPs to create a design with r...
by Abdellah Bakhali
Programmed Complexity

Using HLS To Improve Algorithms
Comparing hand-optimization with tool-based optimization.
October 24, 2019
by Zubair Wadood
Semi Thoughts

Long And Longer Reach SerDes – On The Road Again
Dispatches from the AI Hardware Summit and ECOC 2019.
September 26, 2019
by Mike Gianfagna
Intelligent Analytics

Responsibility And Automotive Security
It's time for the automotive industry to come together to define security bes...
August 22, 2019
by Aileen Ryan
Against The Grain

Make-Or-Break Time For Portable Stimulus
We hear a lot from vendors about the new Portable Stimulus Standard, but how ...
October 25, 2018
by Neil Johnson

Knowledge Centers
Entities, people and technologies explored


  Trending Articles

Power Complexity On The Rise

New architectures, different markets and more variables make it increasingly difficult to design and verify low-power chips.

by Ann Steffora Mutschler

November 2019 Startup Funding

Sixteen startups attracted funding rounds of nine figures in November.

by Jeff Dorsch

Using FPGAs For AI

How good are standard FPGAs for AI purposes, and how different will dedicated FPGA-based devices be from them?

by Brian Bailey

DRAM Scaling Challenges Grow

More nodes and alternative memories are in the works, but schedules remain murky.

by Mark LaPedus

Multi-Patterning EUV Vs. High-NA EUV

Next-gen litho is important for scaling, but it’s also expensive and potentially risky.

by Mark LaPedus

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