System-Level Design

Top Stories

Do Parallel Tools Make Sense?

Experts at the Table, part 2: What can be done instead? And why are companies reluctant to do more in the cloud?

Agile Standards

Standards development has changed from defining everything that might be nice, to a more Agile-like development process.

Faster Verification With AI, ML

With engines improving, the design ecosystem is looking to new approaches to improve productivity.

Why Parallelization Is So Hard

Experts at the Table, part 1: Are we looking to solve the wrong problems? Where does parallelization work best and why.

Debug Issues Grow At New Nodes

Finding the root cause of problems becoming more difficult as systemic complexity rises; methodology and different approaches play an increasingly ...

When Bugs Escape

The ability to find bugs has not kept up with the growing complexity of systems. Bugs are more likely to end up in products than ever before.

Where ML Works Best

Cadence's president talks about machine learning inside and outside of EDA tools, and how to measure the benefits.

Verification As A Flow

Experts at the Table, part 3: How will Portable Stimulus impact SoC verification and what adoption approaches are likely to catch on first?

Design Reuse Vs. Abstraction

IP reuse has reduced the urgency for a higher level of abstraction in complex system-level design, but that still could change.

The Darker Side Of Consolidation

What happens when companies are combined? The outcome often isn't as good as the announcement.

More Top Stories »



Round Tables

Do Parallel Tools Make Sense?

Experts at the Table, part 2: What can be done instead? And why are companies reluctant to do more in the cloud?

Faster Verification With AI, ML

With engines improving, the design ecosystem is looking to new approaches to improve productivity.

Why Parallelization Is So Hard

Experts at the Table, part 1: Are we looking to solve the wrong problems? Where does parallelization work best and why.

Verification As A Flow

Experts at the Table, part 3: How will Portable Stimulus impact SoC verification and what adoption approaches are likely to catch on first?

Verification As A Flow

Experts at the Table, part 2: How did Portable Stimulus get its name, and will it replace UVM?

More Roundtables »



Multimedia

Changing The Design Flow

The rationale for fusing together various pieces of a digital design.

High-Speed SerDes At 7nm

What's changing inside of data centers and how does it affect chip design?

Will FPGAs Work As Expected?

Why equivalence checking is so critical for this market.

M2M’s Network Impact

Why new architectures are required as machines begin talking to machines.

ISO 26262 Statistics

Tech Talk: The statistical underpinnings of safety standards.

More Multimedia »



See All Posts in System-Level Design »

Latest Blogs

Editor's Note

Solving Systemic Complexity

The number of possible interactions is exploding. So why aren't tool companie...
July 26, 2018
What Were They Thinking

A New Era For EDA

Is EDA in decline? Will its fortunes turn around with the end of Moore's Law?
Just A Formality

Functional Safety: Art Or Science?

The market for safety-critical electronics is booming, but development practi...
Frankly Speaking

The Future Is Bright: DARPA Is Driving Electronic Resurgence

Revisiting old ideas leads to new paths forward as changes in technology, arc...
Semi Thoughts

Technical Conferences: The Insurmountable Opportunity

The number of new markets makes it difficult to choose between an expanding a...
Looking Past The Horizon

“Good Enough For Government Work?” Not Anymore.

For more precise static timing analysis with less uncertainty, rethink the id...
A System Perspective

Synthesizing Computer Vision Designs To Hardware

Traditional RTL design flows aren't a good fit for the rapidly changing requi...
Design & Verification

PCIe In High-Performance FPGAs

The value of high performance computing applications depends upon how fast da...
Intelligent Analytics

Bugs With Long Tails Can Be Costly Pests

In the world of servers and HPC, the smallest of inefficiencies can build int...
April 26, 2018
Architect's Diary

Looking For The Elephant In The Valley

Female role models doing exceptional things in tech have always existed. Hope...
March 27, 2018
Against The Grain

Abstracting Abstracter Abstractions In Functional Verific...

With the upcoming Portable Stimulus standard, we need to consider whether abs...
March 26, 2018

Knowledge Centers
Entities, people and technologies explored


  Trending Articles

The Chiplet Race Begins

DARPA and a number of major vendors are backing this modular approach, but hurdles remain.

AI Architectures Must Change

Using the Von Neumann architecture for artificial intelligence applications is inefficient. What will replace it?

Fabs Meet Machine Learning

D2S’ CEO sounds off on the impact of deep learning, EUV and other manufacturing advancements.

Artificial Intelligence Chips: Past, Present and Future

It’s been an uneven path leading to the current state of AI, and there’s still a lot of work ahead.

Chip Aging Becomes Design Problem

Assessing the reliability of a device requires adding more physical factors into the analysis, many of which are interconnected in complex ways.