System-Level Design

Top Stories

Using FPGAs For AI

How good are standard FPGAs for AI purposes, and how different will dedicated FPGA-based devices be from them?

Transforming Silicon Bring-Up

The role of silicon for verification and validation is changing. While there is the desire to Shift Left, silicon also has become a valuable verifi...

Thoroughly Verifying Complex SoCs

With so many variables, verifying complex, heterogenous designs is a task with many tentacles.

Optimizing Hardware Faster

Silexica's CEO talks about why high-level synthesis has become so important across different markets.

Portable Stimulus And Digital Twins

Experts at the Table: How Portable Stimulus plays with the digital twin and the drive toward system-level coverage.

RISC-V Markets, Security And Growth Prospects

Experts at the Table: Why RISC-V has garnered so much attention, what still needs to be done, and where it will likely find its greatest success.

Service Revenue Growing With Chip Complexity

Demand for outside expertise grows with new markets and architectures.

Migrating 3D Into The Mainstream

Experts at the Table: The creation of complex, packaged systems affects everything in the design flow and requires a systems approach.

Rapid Evolution For Verification Plans

While many companies do have verification plans, demands on those plans are changing faster than most companies can evolve.

Utilizing Computational Memory

How processing near memory could change the compute landscape.

More Top Stories »



Round Tables

Portable Stimulus And Digital Twins

Experts at the Table: How Portable Stimulus plays with the digital twin and the drive toward system-level coverage.

RISC-V Markets, Security And Growth Prospects

Experts at the Table: Why RISC-V has garnered so much attention, what still needs to be done, and where it will likely find its greatest success.

Migrating 3D Into The Mainstream

Experts at the Table: The creation of complex, packaged systems affects everything in the design flow and requires a systems approach.

RISC-V Challenges And Opportunities

Who makes money with an open-source ISA, the current state of the RISC-V ecosystem, and what differentiates one vendor from the next.

Extending Portable Stimulus

Experts at the Table: With the initial standard in place, what can we expect in terms of broadening its scope to other domains and applications?

More Roundtables »



Multimedia

Distributed Design Implementation

Simplifying timing closure and sign-off in complex heterogeneous designs.

Finding Hardware Trojans

Why locating security threats in hardware is so difficult.

Which Verification Engine When

How complexity and more data are affecting the design flow.

Visually Assisted Layout In Custom Design

A faster way to optimize designs and find errors.

Signoff-Compatible CDC

Why netlist clock domain crossing is now an essential complement to RTL CDC at advanced nodes and in AI chips.

More Multimedia »



See All Posts in System-Level Design »

Latest Blogs

Just A Formality

OneSpin Users Gather in Munich

Successful event offers opportunity to share tips and technology.
December 2, 2019
Editor's Note

Designing In 4D

Why time is becoming an essential element, and what it means for chip archite...
November 26, 2019
What Were They Thinking

Better, Not Best

There is little point creating the best possible device when slightly better ...
Looking Past The Horizon

Static Verification Of Low Power Designs

The stages of a modern low power development and verification flow.
Frankly Speaking

Verification In The Era Of Autonomous Driving, Artificial...

The importance of data is changing traditional value creation in electronics ...
Design & Verification

Developing Robust Finite State Machines Code With Lint Tools

Revealing finite state machine design bugs at the earliest stages of code dev...
A System Perspective

A Reliable I/O Ring For A Reliable SoC

Integrate disparate I/O ring rules from various IPs to create a design with r...
Programmed Complexity

Using HLS To Improve Algorithms

Comparing hand-optimization with tool-based optimization.
October 24, 2019
Semi Thoughts

Long And Longer Reach SerDes – On The Road Again

Dispatches from the AI Hardware Summit and ECOC 2019.
September 26, 2019
Intelligent Analytics

Responsibility And Automotive Security

It's time for the automotive industry to come together to define security bes...
August 22, 2019
Against The Grain

Make-Or-Break Time For Portable Stimulus

We hear a lot from vendors about the new Portable Stimulus Standard, but how ...
October 25, 2018

Knowledge Centers
Entities, people and technologies explored


  Trending Articles

Power Complexity On The Rise

New architectures, different markets and more variables make it increasingly difficult to design and verify low-power chips.

November 2019 Startup Funding

Sixteen startups attracted funding rounds of nine figures in November.

Using FPGAs For AI

How good are standard FPGAs for AI purposes, and how different will dedicated FPGA-based devices be from them?

DRAM Scaling Challenges Grow

More nodes and alternative memories are in the works, but schedules remain murky.

Multi-Patterning EUV Vs. High-NA EUV

Next-gen litho is important for scaling, but it’s also expensive and potentially risky.