Systems & Design

Top Stories

Silo Busting In The Design Flow
Waterfall development flows no longer work for chip design, but unified tool flows may not be the answer.
Published on November 24th,  2020 by Brian Bailey

Using AI And Bugs To Find Other Bugs
New methodologies are being developed to deal with increasing complexity.
Published on November 24th,  2020 by Ann Steffora Mutschler

Brute-Force Analysis Not Keeping Up With IC Complexity
How to ensure you've dealt with the most important issues within a design, because finding those spots is becoming a lot more important.
Published on November 24th,  2020 by Brian Bailey

Speeding Up AI With Vector Instructions
Uses, challenges and tradeoffs in working with vector engines.
Published on November 4th,  2020 by Ann Steffora Mutschler

Using Verification Data More Effectively
There are more tips and tricks than ever to get the most from verification.
Published on October 29th,  2020 by Ann Steffora Mutschler

Is Hardware-Assisted Verification Avoidable?
Simulation is no longer up to the task of system-level verification, but making the switch to hardware-assisted verification can lead to some surpr...
Published on October 29th,  2020 by Brian Bailey

RISC-V: Will There Be Other Open-Source Cores?
Experts at the Table: The current state of open-source tools, and what the RISC-V landscape will look like by 2025.
Published on October 6th,  2020 by Ed Sperling

System-Level Packaging Tradeoffs
Growing complexity is creating an array of confusing options.
Published on September 30th,  2020 by Ann Steffora Mutschler

Deals That Change The Chip Industry
Nvidia-Arm is just the beginning; more acquisitions are on the horizon.
Published on September 28th,  2020 by Ed Sperling

Have Processor Counts Stalled?
Have chips reached a plateau for the number of processor cores they can effectively make use of? Possibly yes, until you change the programming model.
Published on September 24th,  2020 by Brian Bailey

More Top Stories »



Round Tables

RISC-V: Will There Be Other Open-Source Cores?
Experts at the Table: The current state of open-source tools, and what the RISC-V landscape will look like by 2025.
Published on October 6th,  2020 by Ed Sperling

RISC-V: What’s Missing And Who’s Competing
Experts at the Table: The open-source ISA is gaining ground in multiple markets, but the tool suite is incomplete and the business model is uncertain.
Published on September 23rd,  2020 by Ed Sperling

Creating Better Models For Software And Hardware Verifica...
Experts at the Table: Rethinking approaches for more complex systems, ISAs, and chiplets.
Published on August 4th,  2020 by Ed Sperling

RISC-V Gaining Traction
Experts at the Table: Extensible instruction-set architecture is drawing attention from across the industry and supply chain.
Published on July 30th,  2020 by Ed Sperling

Chip Reliability Vs. Cost
CEO Outlook: Market shifts, higher productivity per engineer and the overhead and opportunities for security and reliability.
Published on July 5th,  2020 by Ed Sperling

More Roundtables »



Multimedia

High-Speed SerDes At 7/5nm
How to place macros inside a PHY in 7/5nm SoCs.
Published on June 2nd,  2020 by Ed Sperling

Rising Packaging Complexity
Why advanced packaging is still so difficult.
Published on May 19th,  2020 by Ed Sperling

Speeding Up Verification Using SystemC
How HLS plus formal can significantly reduce optimization and debug time.
Published on March 23rd,  2020 by Ed Sperling

Timing Closure At 7/5nm
Why shifting left in a complex design is critical.
Published on March 17th,  2020 by Ed Sperling

Banking On FPGA Prototyping
Where the biggest savings are in ASIC design.
Published on March 4th,  2020 by Ed Sperling

More Multimedia »



See All Posts in System-Level Design »

Latest Blogs

What Were They Thinking

What Interested You In 2020
A look back over 2020 to see what you have been reading and the subjects that...
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Frankly Speaking

System Design For Next-Generation Hyperscale Data Centers
New networking and architecture co-design opportunities are creating a fundam...
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Embedded Customization

Impact Of Instruction Memory On Processor PPA
The effect of adding RISC-V extensions to both core size and codesize.
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A System Perspective

ESD P2P And CD Verification Doesn’t Have To Be Hard
Combining geometric and topological data for better reliability verification.
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Looking Past The Horizon

Virtual Prototyping For Power Electronics Systems
Using piecewise linear circuit models rather than models with full SPICE-leve...
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Rule The Bugs

I’m Almost Done
How do you gauge how complete a project is when the last 10% is the hardest p...
October 12, 2020
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Just A Formality

Tackling Functional Correctness, Safety, Trust And Security
IC integrity verification is a major focus at recent and upcoming industry vi...
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Editor's Note

The Next Wave Of Consolidation
Economic conditions are all there. So what's the holdup?
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by Ed Sperling
RISC-V Design Verification

Importance Of A Functional Verification Methodology
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September 24, 2020
by Shubhodeep Roy Choudhury
Sharpening Your Edge

Bridging The Gap Between Driven And Driverless Cars
Why remote control will be a critical link between ADAS and autonomous vehicles.
August 31, 2020
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Design & Verification

Logic Synthesis Basics For FPGA
Combining external and internal synthesis in a tool chain for improved contro...
August 27, 2020
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Knowledge Centers
Entities, people and technologies explored


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