System-Level Design

Top Stories

EDA: 8 Consecutive Years Of Growth
Strength across geographies and tool segments kept revenue strong.
Published on April 4th,  2018 by Ann Steffora Mutschler

Going Deep Or Broad With Formal?
Why formal verification is being used in more ways across more designs.
Published on March 28th,  2018 by Ann Steffora Mutschler

When AI Goes Awry
So far there are no tools and no clear methodology to eliminating bugs. That would require understanding what an AI bug actually is.
Published on March 26th,  2018 by Ed Sperling

Can Big Data Help Coverage Closure?
When does a large amount of data become Big Data, and could system-level verification benefit from it?
Published on March 22nd,  2018 by Brian Bailey

Applying Machine Learning To Chips
Goal is to improve quality while reducing time to revenue, but it's not always so clear-cut.
Published on March 22nd,  2018 by Ann Steffora Mutschler

Merging Verification With Validation
Are these really separate tasks, or just a limitation of tools and flows?
Published on March 22nd,  2018 by Brian Bailey

RISC-V Gains Its Footing
But working with this architecture has some not-so-obvious pitfalls, and new tools licensing options may be necessary.
Published on February 26th,  2018 by Ann Steffora Mutschler

Debugging Debug
Can time spent in debug be reduced?
Published on February 22nd,  2018 by Brian Bailey

Using Data Mining Differently
As the amount of data continues to rise, so does the ability to do something useful with it.
Published on February 22nd,  2018 by Ann Steffora Mutschler

Verification Of Functional Safety
Part 2 of 2: How should companies go about the verification of functional safety and what tools can be used?
Published on February 22nd,  2018 by Brian Bailey

More Top Stories »



Round Tables

Could Liquid IP Lead To Better Chips?
Experts at the Table, part 3: What remains to be done before liquid IP becomes a standard practice? What issues are preventing adoption today?
Published on January 9th,  2018 by Brian Bailey

Which Verification Engine?
Experts at the table, part 3: The value of multiple verification engines, and what's driving demand for verification in the cloud.
Published on January 2nd,  2018 by Ed Sperling

Custom Vs. Non-Custom Design
Experts at the table, part 1: Decisions about whether to customize vary by market, the size of companies, and in some cases whether off-the-shelf p...
Published on December 21st,  2017 by Ed Sperling

Could Liquid IP Lead To Better Chips?
Experts at the Table, part 2: What is the business model associated with liquid IP and what can we expect to migrate and which blocks will remain a...
Published on December 13th,  2017 by Brian Bailey

Which Verification Engine?
Experts at the Table, part 2: The real value of multiple verification engines; cloud-based verification gains some footing, particularly with inter...
Published on December 6th,  2017 by Ed Sperling

More Roundtables »



Multimedia

Tech Talk: Automotive Design
How to speed up time to market while improving quality in automotive chips.
Published on March 22nd,  2018 by Ann Steffora Mutschler

Tech Talk: Faster Simulation
Why simulation is still so important and how to make it run faster.
Published on March 22nd,  2018 by Ann Steffora Mutschler

Tech Talk: 5/3nm Parasitics
What to expect at future process nodes.
Published on February 22nd,  2018 by Ed Sperling

Tech Talk: Verification
How verification will change as chips are used in machine learning, medical, 5G, and what impact advanced packaging will have on all of this.
Published on November 30th,  2017 by Ed Sperling

Tech Talk: Pseudo SRAM
A different way to improve performance at the most advanced nodes.
Published on October 26th,  2017 by Ed Sperling

More Multimedia »



See All Posts in System-Level Design »

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