category: A System Perspective

category: Auto, Security & Edge AI

Automating Traditional PCB Layout Verification With Electrically Based Design Rule Checks
By Rory Riggs - 28 May, 2026 - Comments: 0

Electrical verification and sign-off of a printed circuit board (PCB) is a challenging, tedious, and manual process. If time permits, this visual inspection to catch errors that might cause costly respins is done throughout the PCB layout process, but traditionally it is performed only once at the end of the design cycle. This approach creates significant project delays when issues are discover... » read more

Transforming DRC Closure At Advanced Nodes
By James Paris - 30 Apr, 2026 - Comments: 0

If you’re working on SoCs at 2 nm or below, you know DRC is a different beast these days. Early in the design, it’s common for DRC runs to dump hundreds of millions—or even billions—of violations at your feet. And that’s when everything is changing fast: block interfaces aren’t fixed and constraints are shifting with every new iteration. Making sense of these massive result sets, fi... » read more

Precision In Depth: Extraction Workflows For CFETs And Buried Power Rails
By Karen Chow - 26 Mar, 2026 - Comments: 0

By Karen Chow, Sheetal Veronica, and Kunjesh Agashiwala In the heart of Manhattan, where land is scarce but demand is infinite, architects had to rethink the city grid. Instead of sprawling outward, they built upward with skyscrapers and carved subways below ground, inventing a “3D” city. Today’s chip designers face a similar dilemma: the two-dimensional plane of planar scaling is near... » read more

An Integrated Workflow For Circuit Design, Simulation, And Functional Safety Analysis
By Daniel Zhang - 26 Feb, 2026 - Comments: 0

By Daniel Zhang and Claudius Jordan Functional safety analysis is a crucial step in the development of safety-critical systems. It ensures that the system-under-development meets its defined safety requirements and functions safely under both nominal and fault conditions. In the event of a failure, the system must respond appropriately to mitigate the risk of safety hazards that could potent... » read more

Opening The Door To STCO: Hierarchical Device Planning
By Todd Burkholder - 29 Jan, 2026 - Comments: 0

By Todd Burkholder and Per Viklund The heterogeneous integration of multiple chiplets in a single packaging platform is critical for many high-performance market segments, such as AI, hyperscalers, high-performance computing, cloud data centers, neural processors, and even autonomous vehicles. This increased design complexity has led to an explosion in device complexity and pin counts. It... » read more

Managing Complexity: Evolving Approaches To Design Rule Checking In Modern IC Design
By John Ferguson - 23 Dec, 2025 - Comments: 0

As integrated circuit (IC) designs have grown in complexity, scale and speed requirements, design rule checking (DRC) has evolved from a routine step into a critical pillar of successful tapeouts. Foundry rules, shrinking geometries and advanced patterning have increased both the engineering effort and computational overhead needed for verification. Today, DRC isn’t just about sign-off—it... » read more

Securing IP Integrity In Advanced SoC Design
By Sara Khalaf - 25 Nov, 2025 - Comments: 0

In today’s complex system-on-chip (SoC) design flows, intellectual property (IP) blocks are everywhere—licensed from third parties, leveraged from internal libraries, or hand-crafted by expert teams. These IPs are typically delivered in a “black box” format and are expected to remain unchanged throughout the physical design stages, from initial floorplanning to top-level placement, rout... » read more

Smart Handling Of Reset Domain Crossings To Non-Resettable Flip-Flops
By Reetika - 30 Oct, 2025 - Comments: 0

As system-on-chip (SoC) designs evolve, they aren’t just getting bigger — they’re becoming more intricate. One of the trickiest challenges in this evolution lies in handling resets. Today’s architectures often juggle multiple asynchronous reset sources alongside sequential elements such as non-resettable registers (NRRs), which operate without dedicated reset pins. When a signal crosses... » read more

How Multiphysics Is Powering The Future Of 3D-ICs
By John Ferguson - 29 Sep, 2025 - Comments: 0

It’s surprising to learn that the idea of 3D integrated circuits (3D ICs) has been kicking around for over sixty years. Not long after the first MOS IC emerged in 1960, researchers were already thinking vertically. By 1983, Fujitsu manufactured the first 3D IC prototype using through-silicon via (TSV) technology, using laser beam recrystallization. That’s a long time for a good idea to catc... » read more

How To Transform Verification Time-To-Results
By Priyank Jain - 28 Aug, 2025 - Comments: 0

The clock is ticking. Your team has just completed another full-chip DRC run on a complex 5nm SoC, and the results are overwhelming: millions of violations across hundreds of blocks. With tape-out deadlines approaching, you need to quickly identify which issues are critical, which are systematic and which blocks require immediate attention. Every day spent in DRC debug is a day delayed to marke... » read more

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