ESD P2P And CD Verification Doesn’t Have To Be Hard


As a designer or verification engineer, you’re fighting the effects of electrostatic discharge (ESD) in your integrated circuit (IC) designs all the time. ESD is one of those frustrating issues that can challenge even the most experienced designers. Once an IC is in the market, unexpected electrical shorts will cause immediate failure or dielectric breakdown will result in gradual circuit deg... » read more

Solving CSD Verification Challenges


To tackle power consumption and slow execution, modern computational storage devices (CSD) seek to reduce data movement by including a small processing element next to the CSD (figure 1). The data request from the host is executed locally by the processing element, data is locally manipulated, and the result sent back to the host. Much less data is exchanged between storage and host, thus savin... » read more

Innovative Strategies Are Improving Early Design Circuit Verification


Layout vs. schematic (LVS) circuit verification is an essential stage in the integrated circuit (IC) design verification cycle. However, given today’s large design sizes, numerous hierarchies, and complex foundry decks, meeting planned tapeout deadlines in the quickest turnaround time (TAT) can be difficult. In an effort to minimize TAT, most design teams now use parallelized design flows, wh... » read more

Radio Frequency Technology Is Found Everywhere In Daily Life


By Greg Curtis and YuLing Lin Innovation is everywhere around us. From high-performance computing, communications, autonomous driving, and the Internet of Things (figure 1), each segment has led to a rapid increase in design innovation. This innovation has been particularly true in communications, as Radio Frequency (RF) technology is found everywhere in daily life. RF technology is critical... » read more

Running With O-RAN


5G standards are opening the world of hardware development to anyone that can build the best, cost-effective products. At the heart of many of those products is the system on a chip (SoC) that needs to be verified within the context of the overall system. Many new companies are in 5G chip development now, delivering custom solutions that match the many configurations need for different rural an... » read more

Post Layout Simulation Is Becoming The Bottleneck For Analog Verification


My, have times changed. I remember when I first started out as a green analog designer right out of college, we would cut rubylith masking film on a large light table representing the different layers of our design to generate the design for manufacturing of the chip. We proactively worked to mitigate cross coupling of noise to our signal nets, but we were rarely concerned about interconnect re... » read more

Lower Resistance Protects Against Failure In IC Design


By Fady Fouad, Esraa Swillam, and Jeff Wilson When you’re fighting off a threat, you typically want all the resistance you can muster. In IC design, on the other hand, minimizing resistance is crucial to success in power structure design. As metals get narrower with technology node advances, resistance levels rise, and voltage drop (IR) and electromigration (EM) issues grow, both in number... » read more

5G Brings New Verification Challenges


In the summer of 2018, Siemens raised a few eyebrows within the verification community when we acquired Sarokal, based in Finland. What that community did not piece together at the time was that Sarokal is the leader in 5G testing and has a seasoned team of people that have work closely with leading telecommunication companies to provide hardware and software solutions for fronthaul system test... » read more

EDA In The Cloud


Interest in the use of third-party public clouds in conjunction with electronic design automation (EDA) applications has never been higher. Back in February, Ed Sperling and I did a video interview (embedded below) to discuss EDA and cloud computing. This article follows up on that interview, providing some additional insight into why and how the integrated circuit (IC) industry reached this po... » read more

Timing Library LVF Validation For Production Design Flows


Variation modeling has evolved over the past several years from a single derating factor that represents on-chip variation (OCV), to Liberty Variation Format (LVF), today’s leading standard format that encapsulates variation information in timing libraries (.libs). LVF data is considered a requirement for advanced process nodes 22nm and below. At the smallest process nodes such as 7nm and ... » read more

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