Get To Know The Gate-Level Power Aware Simulation


The post-synthesis gate-level netlist (GL-netlist) based PA simulation input requirements are mostly the same as RTL simulation. However, the design under verification here is the GL-netlist from synthesis, so logic gates from standard, MV and Macro cell Liberty libraries are already inserted or instantiated in the design. Hence power aware simulation (PA-SIM) at post-synthesis also requires Li... » read more

Collaborative Multi-Board System Design


Designing electronic systems has become measurably more complex during the past decade. Many of the products that are developed today are in-fact complex interconnected systems. Using the automotive market as an example, the first level of a system is an element; an individual component or sub-assembly that is designed to be part of a larger collaborating function. At the next level is the sub-... » read more

Achieving Separation On Multiprocessor SoCs For Enhanced Safety And Security


As I read my colleague Andrew Caples’ article on The Blurring of Safety and Security for Embedded Devices, I immediately started to think of the Xilinx UltraScale+ MPSoC – as I have engaged with numerous customers about using this chip for both safety and security purposes, and the requirements for both areas are definitely starting to blur. I quickly realized a blog about the Xilinx... » read more

ON Semiconductor Meets AEC Challenges With Electrothermal Analysis


By Justin Yerger, ON Semiconductor, and Ahmed Eisawy, Mentor, a Siemens Business ON Semiconductor is a leading provider of products for automotive applications that follow the Automotive Electronics Council (AEC Q-100-012) requirements for reliability characterization of smart power devices. In particular, Automotive Smart FET driver ICs present verification challenges when verifying short c... » read more

Huawei Delivers Outstandingly Accurate Models


By John Parry, Mentor, a Siemens Business, and Yake Fang, Huawei Technologies Co., Ltd. Packaging high-performance multi-core IC devices used in communication applications is a key challenge for both manufacturers and system integrators. Traditionally a System-in-Package (SiP) has been taken, with chips mounted side-by-side, allowing differing semiconductor technologies to be mixed. More r... » read more

Mathematic Model Helps Predict Markets That Will Drive Semiconductor Growth


Which markets will drive semiconductor growth in the coming years and for how long are key questions that Wally Rhines, CEO of Mentor, a Siemens Business, strove to answer in a thought-provoking Mentor User2User Conference keynote here in Santa Clara, CA. To a packed auditorium Rhines described how a tried-and-true mathematical method can be applied to more accurately forecast growth and longev... » read more

IoT Edge Design Demands A New Approach


A new breed of designers has arrived that is leveraging the advances in sensing technology to build the intelligent systems at the edge of the IoT. These systems play in every space: on your body, at home, the car or bus that you take to work, and the cities, factories, office buildings, or farms that you work. The energy that you consume and how you travel, by air, land, or sea, all have IoT e... » read more

IP Qualification During RTL Synthesis


By Sudhakar Jilla and Arvind Narayanan The use of IP (intellectual property) as basic building blocks is an established practice for SoC designs. Most IP is developed without chip-level context and very little knowledge about physical design, which can introduce unwanted schedule risk into the design process. Much of the risk of IP development can be mitigated by using new physical synthesis... » read more

Real-Time Performance Across The Factory Floor


Next generation processors continue to push the performance envelope. It seems the price continues to drop while the processing speeds increase with each new processor release. I recall discussions not that long ago in which the future utility of real-time operating systems and middleware were being bantered about as if they were not going to be required going forward. After all, with each subs... » read more

Transistor-Level Defect Diagnosis


Each new semiconductor process node represents exciting opportunities for suppliers of design, manufacturing, test, and failure analysis solutions. A new process means new challenges to solve, and hopefully more money to be made. On the flip side, whenever solutions that address these new challenges are presented, we seldom hear how useful these are to more mature process nodes. One technology ... » read more

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