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Mastering FOWLP And 2.5D Design Is Easier Than You Think


IC packaging has come into its own, where once traditional packaging was a “necessary evil,” today’s packaging can add significant value. There is an increase in functional density and flexibility by providing a platform for heterogeneous design assembly. Where designs implemented in an SoC can become too large to yield satisfactorily and too difficult to implement on one process node, pa... » read more

Considering The Power Of The Cloud For EDA


By Michael White, Siemens EDA, in technical collaboration with Peeyush Tugnawat, Google Cloud, and Philip Steinke, AMD At DAC 2022, Google Cloud, AMD, and Calibre Design Solutions presented an EDA in the cloud solution that enables companies to access virtually unlimited compute resources when and as needed to optimize their design and verification flows. If your company is considering addin... » read more

Debug This! How To Simplify Coverage Analysis And Closure


For years the process of ASIC and FPGA design and verification debug consisted primarily of comprehending the structure and source code of the design with waveforms showing activity over time, based on testbench stimulus. Today, functional verification is exponentially complex with the emergence of new layers of design requirements (beyond basic functionality) that did not exist years ago — f... » read more

Why Every Design IP Needs A Complete QA Methodology


Design IP is a key contributor to innovation in the semiconductor industry today. As the complexity and scale of silicon designs increase, so does design and verification time. Design IP enables modularization and re-use of design components, so that designers can leverage already-existing components as a baseline to accelerate design schedules. Therefore, it is not surprising that the usage of... » read more

The Complex Art Of Handling S-Parameters


By Pradeep Thiagarajan and Youssef Abdelkader IC design is transforming at an accelerated pace along with fabrication technology. The need to incorporate more functionality has led to denser dies, multi-die chips, stacked 3D ICs, and advanced packaging. Furthermore, the increasing demand for enhanced connectivity with more and faster access to data continues to drive technology towards highe... » read more

Earlier SoC Design Exploration And Verification Gets Better Designs To Tapeout Faster


By Nermeen Hossam and John Ferguson Between the complexity of advanced node design verification and the competition to be first to the market, system-on-chip (SoC) designers no longer have the luxury of waiting until each sub-block of a chip is DRC-clean to start their chip assembly and verification. Today’s SoC designers typically start chip integration in parallel with block development.... » read more

2.5/3D IC Reliability Verification Has Come A Long Way


2.5D/3D integrated circuits (ICs) have evolved into an innovative solution for many IC design and integration challenges. As shown in figure 1, 2.5D ICs have multiple dies placed side-by-side on a passive silicon interposer. The interposer is placed on a ball grid array (BGA) organic substrate. Micro-bumps attach each die to the interposer, and flip-chip (C4) bumps attach the interposer to the ... » read more

High-Performance 5G IC Designs Need High-Performance Parasitic Extraction


By Karen Chow and Salma Ahmed Elhenedy We are rapidly approaching a future where 5G telecommunications will be the norm. With its increased data speeds and bandwidth, 5G has the potential to change the way we live our lives. But what does that mean for the average person? Think about cellphones, for one. You don't just use your phone for calling or texting anymore—you surf the web, chec... » read more

The Evolving Digital Journey Of The Electronics Value Chain


Digitally transforming how the electronics value chain is traversed will unlock the full innovative potential of system design companies all over the world. By augmenting desktop authoring tools with integrated, native cloud applications that seamlessly connect companies with the electronics value chain, design teams will be empowered to confidently deliver on aggressive requirements, schedules... » read more

Formal Verification Ensures The Perseverance Rover Lands Safely On Mars


By Joe Hupcey III and Kevin Campbell Safely landing a spacecraft anywhere on Mars is a complex, high-risk challenge. Even worse, the most scientifically interesting areas of the planet are guarded by boulders, ditches, and tall cliffs — land formations that aren’t very welcoming to vehicles. Such was the case with the Mars Perseverance Rover's Landing Site: Jezero Crater. It’s not an e... » read more

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