Running With O-RAN


5G standards are opening the world of hardware development to anyone that can build the best, cost-effective products. At the heart of many of those products is the system on a chip (SoC) that needs to be verified within the context of the overall system. Many new companies are in 5G chip development now, delivering custom solutions that match the many configurations need for different rural an... » read more

Post Layout Simulation Is Becoming The Bottleneck For Analog Verification


My, have times changed. I remember when I first started out as a green analog designer right out of college, we would cut rubylith masking film on a large light table representing the different layers of our design to generate the design for manufacturing of the chip. We proactively worked to mitigate cross coupling of noise to our signal nets, but we were rarely concerned about interconnect re... » read more

Lower Resistance Protects Against Failure In IC Design


By Fady Fouad, Esraa Swillam, and Jeff Wilson When you’re fighting off a threat, you typically want all the resistance you can muster. In IC design, on the other hand, minimizing resistance is crucial to success in power structure design. As metals get narrower with technology node advances, resistance levels rise, and voltage drop (IR) and electromigration (EM) issues grow, both in number... » read more

5G Brings New Verification Challenges


In the summer of 2018, Siemens raised a few eyebrows within the verification community when we acquired Sarokal, based in Finland. What that community did not piece together at the time was that Sarokal is the leader in 5G testing and has a seasoned team of people that have work closely with leading telecommunication companies to provide hardware and software solutions for fronthaul system test... » read more

EDA In The Cloud


Interest in the use of third-party public clouds in conjunction with electronic design automation (EDA) applications has never been higher. Back in February, Ed Sperling and I did a video interview (embedded below) to discuss EDA and cloud computing. This article follows up on that interview, providing some additional insight into why and how the integrated circuit (IC) industry reached this po... » read more

Timing Library LVF Validation For Production Design Flows


Variation modeling has evolved over the past several years from a single derating factor that represents on-chip variation (OCV), to Liberty Variation Format (LVF), today’s leading standard format that encapsulates variation information in timing libraries (.libs). LVF data is considered a requirement for advanced process nodes 22nm and below. At the smallest process nodes such as 7nm and ... » read more

Balancing Flexibility And Quality In SRAM Verification


Memory is an essential component of system-on-chip (SOC) designs, especially at advanced nodes. SoCs use a variety of memory block types, such as static random-access memory (SRAM) and dynamic RAM (DRAM), to perform computations. The SRAM blocks, which consist of an assembly of specialized calls that abut or overlap one another in a specific arrangement that complies with the circuit specificat... » read more

Cloud Characterization


Library characterization is a compute-intensive task that takes days to weeks to complete. Runtimes for library characterization are increasing due to larger library sizes, higher number of operating conditions to characterize, as well as the need for statistical variation modeling in libraries at 22/20nm and smaller process nodes. Cloud platforms offer a way to accelerate library characterizat... » read more

A Reliable I/O Ring For A Reliable SoC


What is an input/output (I/O) ring, and why should I care about it? If you’re a system-on-chip (SoC) designer, you had better know the answer to that question. SoCs are the darlings of the semiconductor industry—they combine all the typical functionality of a computer (central processing unit (CPU), memory, input/output (I/O) ports, and storage) on a single chip. They’re particularly popu... » read more

5G Needs Cohesive Pre- And Post-Silicon Verification


While 5G doesn’t start from a clean slate, it does make significant changes to the 4G architecture. These changes mean that the ecosystem from chips to operators is evolving, giving opportunities to more companies to engage in this growing market. Realignment in fronthaul, midhaul and backhaul In particular, the radio access network (RAN) has been redefined as Cloud RAN (sometimes called ... » read more

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