5nm Design Progress


Activity surrounding the 5nm manufacturing process node is quickly ramping, creating a better picture of the myriad and increasingly complex design issues that must be overcome. Progress at each new node after 28nm has required an increasingly tight partnership between the foundries, which are developing new processes and rule decks, along with EDA and IP vendors, which are adding tools, met... » read more

Week In Review: Manufacturing, Test


Chipmakers GlobalFoundries said that the company’s 22nm FD-SOI technology has delivered more than $2 billion worth of client design win revenue. With more than 50 total client designs, the technology is designed for automotive, 5G connectivity and the Internet of Things (IoT). Helic has announced that its electromagnetic (EM) modeling engine has been certified for GlobalFoundries’ 22nm ... » read more

Bridges Vs. Interposers


The number of technology options continue to grow for advanced packaging, including new and different ways to incorporate so-called silicon bridges in products. For some time, Intel has offered a silicon bridge technology called Embedded Multi-die Interconnect Bridge (EMIB), which makes use of a tiny piece of silicon with routing layers that connects one chip to another in an IC package. In ... » read more

Week In Review: Manufacturing, Test


Chipmakers and OEMs Fujitsu Semiconductor and United Microelectronics Corp. (UMC) announced that UMC will acquire all of the shares of Mie Fujitsu Semiconductor Limited (MIFS), a 300mm wafer foundry joint venture between both companies. In addition to the 15.9% of MIFS shares currently owned by UMC, Fujitsu Semiconductor will transfer the remaining 84.1% of its shares in MIFS to UMC, making MI... » read more

Blog Review: June 27


Applied Materials' Sundeep Bajikar argues that to realize the full potential of AI, new computing architectures are necessary, otherwise AI will quickly become unaffordable. Synopsys' Iain Singleton considers why it may not always be necessary to start at the reset state during formal verification and how to use abstractions to get a head start on bug hunting. Cadence's Meera Collier look... » read more

Materials, Magnetism & Quantum Physics


For the past half-century, chipmakers have been following the same roadmap for improving performance in chips and reducing the cost of chips. That has proven tremendously effective in reducing costs and packing computing into a smaller space, allowing people to carry around what used to be a multi-million-dollar mainframe in their pocket. That approach is beginning to lose momentum. It's ge... » read more

System-In-Package Vs. eNVM


The booming automotive and IoT markets are driving increasing demand for microcontrollers (MCUs). Recent forecasts project that the overall MCU compound annual growth rate (CAGR) will reach 4% over the next five years, and in particular the automotive MCU CAGR could reach close to 14%. Non-volatile memory (NVM) is a critical element of MCUs, as it is needed not only to store the code, but al... » read more

Dealing With Resistance In Chips


Chipmakers continue to scale the transistor at advanced nodes, but they are struggling to maintain the same pace with the other two critical parts of the device—the contacts and interconnects. That’s beginning to change, however. In fact, at 10nm/7nm, chipmakers are introducing new topologies and materials such as cobalt, which promises to boost the performance and reduce unwanted resist... » read more

Tech Talk: Connected Intelligence


Gary Patton, CTO at GlobalFoundries, talks about computing at the edge, the slowdown in scaling, and why new materials and packaging approaches will be essential in the future. https://youtu.be/Zbz0R_yFFrQ » read more

Big Trouble At 3nm


As chipmakers begin to ramp up 10nm/7nm technologies in the market, vendors are also gearing up for the development of a next-generation transistor type at 3nm. Some have announced specific plans at 3nm, but the transition to this node is expected to be a long and bumpy one, filled with a slew of technical and cost challenges. For example, the design cost for a 3nm chip could exceed an eye-p... » read more

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