From Future Vision To Running Hardware: Verification At DAC 2026


At last year's DAC in San Francisco, I sat in "A Look into the Future of Verification," an Engineering Track special session debating where our discipline is headed — multi-language flows, AI co-pilots, portable stimulus, formal methods. The discussion was energizing, and what struck me then stayed with me since: whatever that future looks like, it has to execute somewhere. And increasingly, ... » read more

Why Chip Engineers Should Care About AI-Created Behavioral Models


You probably know this bottleneck too well: full transistor-level or physical simulations—whether analog circuit, electromagnetic, or thermal—can take weeks or even months. For complex designs, simulating every internal transistor in every block quickly becomes impractical. This is why creating accurate behavioral models is so important. A good behavioral model captures a block's input-o... » read more

The Impact Of AI Automation On Chip Design


Key Takeaways: Tools are currently built with a defined notion of how they will be used. For agentic solutions they will be transformed into collections of callable engines. Agents may be built by EDA companies for design houses or larger design houses may build their own, potentially transforming the EDA business model. The role of engineers will change, but exactly how is not certa... » read more

The End Of Physics Silos In Engineering AI


Modern engineering software was built around an assumption that made sense for its time: different physics problems required different tools, solvers, and workflows. Structural analysis lived in one environment. Thermal modeling lived in another. Electromagnetics lived in a different stack. Over time, engineering workflows became fragmented into isolated software systems, disconnected solver... » read more

Data Center Chokepoints Tied To AI, Political Pressure, Supply Chain


Key Takeaways: AI-driven compute demands have led to several distinct supply chain bottlenecks for data centers. With data center energy demand surging faster than the grid can scale, small nuclear power has quickly moved to the center of the conversation. Hyperscalers have leaned into specialized facility design to meet their challenges, leading to an increasingly fragmented semicon... » read more

From Feature-Scale Simulation To Digital Twins: Helping Process Engineers Tackle Growing Complexity


For process engineers facing rising manufacturing complexity, physics-based simulation provides the foundation for understanding what is happening on the wafer. AI, automation, and digital twins become powerful only when they build on that foundation, enabling faster exploration without losing trust, calibration, or engineering judgment. The growing challenge of semiconductor manufacturing Se... » read more

AI In Chip Design: Lots Of Promise, Plenty Of Unanswered Questions


Key Takeaways: AI opens the door to exploring a much larger solution space, similar to what high-level synthesis did years ago, but questions persist about the impact of increasing reliance on what is essentially a black-box chip design. There is no consistent answer to how successful AI will be, where it will succeed or fail, or how it will apply to different markets and EDA customers.... » read more

Change Is Tough


When I was actively involved in the creation of standards for the EDA and semiconductor industry, it was often joked that the great thing about standards is that there are plenty to choose from. According to the Internet, this quote can either be attributed to Grace Murray Hopper (an incredible pioneer in the development of modern programming languages and a rear admiral in the Navy), or Andrew... » read more

Innovation First, AI Second: Lessons From SSN And The Future Of Test


By Marc Hutner and Ron Press Artificial Intelligence is rapidly becoming pervasive in society and across semiconductor development processes. We have to be careful not to apply AI to solve optimizations and challenges of existing methods but pair with engineering innovation for evolutionary results. One example is the application of scan test data in multi-core designs. AI can optimize the d... » read more

Rethinking Ethernet For The AI Scale-Up Era: Inside ESUN


Every generation of AI infrastructure has redefined what "the network" means. In today's training clusters — scaling from hundreds to hundreds of thousands of accelerators — the interconnect is no longer a supporting actor. It has become a first-order determinant of system throughput, utilization, and cost per token. Accelerators inside these systems don't just move data; they synchronize o... » read more

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