Shrinking LLMs With Self-Compression


Language models are becoming ever larger, making on-device inference slow and energy-intensive. A direct and surprisingly effective remedy is to prune complete channels whose contribution to the task is negligible. Our earlier work introduced a training-time procedure – Self-Compression [1, 4] – that lets back-propagation decide the bit-width of every channel, so unhelpful ones fade away. T... » read more

AI: A New Tool For Hackers, And For Preventing Attacks


Semiconductor Engineering sat down to discuss hardware security challenges, including new threat models from AI-based attacks, with Nicole Fern, principal security analyst at Keysight; Serge Leef, AI-For-Silicon strategist at Microsoft; Scott Best, senior director for silicon security products at Rambus; Lee Harrison, director of Tessent Automotive IC Solutions at Siemens EDA; Mohit Arora, seni... » read more

The Complete Guide To Intelligent Edge Technology


The rise of edge technology is transforming how data is processed and decisions are made, right where data is generated. Unlike traditional cloud computing, intelligent edge computing pushes processing closer to the source, enabling faster responses and improved efficiency. The global edge AI market reflects this shift, which was valued at $20.78 billion in 2024. By 2030, it's projected to gro... » read more

Democratizing Design: How The CHIPS Act Is Reshaping EDA And Semiconductor Innovation


After 26 years in the electronics industry, I've witnessed countless technological shifts, but few have been as transformative — or as promising — as what we're experiencing with the CHIPS Act. I spoke at a recent 62nd DAC panel discussion alongside industry colleagues Saverio Fazzari from Booz Allen Hamilton and Vivek Prasad from a non-profit organization established to operate the Nationa... » read more

Novel Assembly Approaches For 3D Device Stacks


The next big leap in semiconductor packaging will require a slew of new technologies, processes, and materials, but collectively they will enable orders of magnitude improvement in performance that will be essential for the AI age. Not all of these issues are fully solved but the recent Electronic Components Technology Conference (ECTC) provided a glimpse into the huge leaps in progress that... » read more

Iteration And Hallucination


Iteration loops have been a vital aspect of EDA flows for decades. Ever since gate delays and wire delays became comparable, it became necessary to find out if the result of a given logic synthesis run would yield acceptable timing. Over the years this problem became worse because one decision can affect many others. The ramifications of a decision may not have been obvious to an individual too... » read more

Mixed Messages Complicate Mixed-Signal


Several years ago, analog and mixed signal (AMS) content hit a wall. Its contribution to first-time chip failure doubled, and there is no evidence that anything has improved dramatically since then. Some see that the problem is likely to get worse due to issues associated with advanced nodes, while others see hope for improvement coming from AI or chiplets. Fig. 1: Cause of ASIC respins. S... » read more

Redefining SoC Design: The Shift To Secure Chiplet-Based Architectures


The semiconductor industry is undergoing a paradigm shift from monolithic system-on-chip (SoC) architectures to modular, chiplet-based designs. This transformation is driven by escalating design complexity, soaring fabrication costs, and the relentless pursuit of efficiency. However, as chiplet adoption accelerates, security becomes a critical concern, requiring robust measures to protect data,... » read more

EDA’s Top Execs Map Out An AI-Driven Future


Artificial intelligence is permeating the entire semiconductor ecosystem, forcing fundamental changes in AI chips, the design tools used to create them, and the methodologies used to ensure they will work reliably. This is a global race that will redefine nearly every domain over the next decade. In presentations and interviews over the past several months, top EDA executives converged on th... » read more

Power Delivery Challenges For AI Chips


As artificial intelligence (AI) workloads grow larger and more complex, the various processing elements being developed to process all that data are demanding unprecedented levels of power. But delivering this power efficiently and reliably, without degrading signal integrity or introducing thermal bottlenecks, has created some of the toughest design and manufacturing challenges in semiconducto... » read more

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