More Knobs, Fewer Markers


The next big thing in chip design may be really big — the price tag. In the past, when things got smaller, so did the cost per transistor. Now they are getting more expensive to design and manufacture, and the cost per transistor is going up along with the number of transistors per area of die, and in many cases even the size of the die. That's not exactly a winning economic formula, which... » read more

Uses And Limitations Of AI In Chip Design


Raik Brinkmann, president and CEO of OneSpin Solutions, sat down with Semiconductor Engineering to talk about AI changes and challenges, new opportunities for using existing technology to improve AI, and vice versa. What follows are excerpts of that conversation. SE: What's changing in AI? Brinkmann: There are a couple of big changes underway. One involves AI in functional safety, where y... » read more

Using Hypervisor For IVI And AUTOSAR Consolidation On An ECU


Current approaches used to tackle the complexities described earlier in this paper (cockpit domain units) are both cost-prohibitive and lacking in performance. Utilizing virtualization in automotive software architecture provides a better approach when taking on these complexities. This can be achieved by encapsulating different heterogeneous automotive platforms inside virtual machines running... » read more

Scaling, Packaging, And Partitioning


Prior to the finFET era, most chipmakers either focused on shrinking or packaging, but they rarely did both. Going forward, the two will be inseparable, and that will lead to big challenges with partitioning of data and processing. The key driver here, of course, is that device scaling no longer provides appreciable benefits in power, performance and cost. Nevertheless, scaling does provide ... » read more

Making Sense Of Inferencing Options


Ian Bratt, fellow in Arm’s machine learning group, sheds light on all the different processing elements in machine learning, how different end user requirements affect those choices, why CPUs are a critical element in orchestrating what happens in these systems, and how power and software play into these choices. » read more

Addressing Pain Points In Chip Design


Semiconductor Engineering sat down to discuss the impact of multi-physics and new market applications on chip design with John Lee, general manager and vice president of ANSYS' Semiconductor Business Unit; Simon Burke, distinguished engineer at Xilinx, Duane Boning, professor of electrical engineering and computer science at MIT; and Thomas Harms, director EDA/IP Alliance at Infineon. What foll... » read more

Software Support Scenarios


Do you need support for your software? Let’s look at 3 scenarios to explore the question. Using software that is single version Using software that is developed in house Using Software as a Service. These are not the only models or cases out there but will allow us to explore some of the main factors involved. Using software that is single version: Maybe it is a pa... » read more

Migrating 3D Into The Mainstream


Semiconductor Engineering sat down to discuss changes required throughout the ecosystem to support three-dimensional (3D) chip design with Norman Chang, chief technologist for ANSYS' Semiconductor Business Unit; John Park, product management director for IC packaging and cross-platform solutions at Cadence; John Ferguson, director of marketing for DRC applications at Mentor, a Siemens Business;... » read more

RISC-V Challenges And Opportunities


Semiconductor Engineering sat down to discuss open instruction set hardware and the future of RISC-V with Ben Levine, senior director of product management in Rambus' Security Division; Jerry Ardizzone, vice president of worldwide sales at Codasip; Megan Wachs, vice president of engineering at SiFive; and Rishiyur Nikhil, CTO of Bluespec. What follows are excerpts of that conversation. (L-... » read more

Solving The Memory Bottleneck


Chipmakers are scrambling to solve the bottleneck between processor and memory, and they are turning out new designs based on different architectures at a rate no one would have anticipated even several months ago. At issue is how to boost performance in systems, particularly those at the edge, where huge amounts of data need to be processed locally or regionally. The traditional approach ha... » read more

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