Blog Review: Aug. 15


Cadence's Paul McLellan checks out what's driving the growth of China's semiconductor industry plus the state of fab construction, from a CAPSA presentation by SEMI's Lung Chu. Mentor's Joe Hupcey III has some tips for how to handle inconclusive results in formal verification, starting with how to identify where the analysis got stuck. Synopsys' Taylor Armerding listens in on a presentati... » read more

Do Parallel Tools Make Sense?


Semiconductor Engineering sat down to talk about parallelization efforts within EDA with Andrea Casotto, chief scientist for Altair; Adam Sherer, product management group director in the System & Verification Group of Cadence; Harry Foster, chief scientist for Mentor, a Siemens Business; Vladislav Palfy, global manager for applications engineering at OneSpin; Vigyan Singhal, chief Oski for ... » read more

Week In Review: Design, Low Power


Achronix and Mentor uncorked an optimized HLS flow for Achronix's FPGA technology products. The integrated development environment enables designers to quickly go from C++ to FPGA using Mentor's Catapult HLS and Achronix's ACE design tools. Initially used for 5G wireless applications to reduce the overall development effort and improve QoR, it is suitable for any design targeting Achronix techn... » read more

Getting Ahead With Early Power Analysis


Today’s mobile applications need to cater to a broad set of applications. They can be communications-heavy (Bluetooth and GPS), graphics-intensive (streaming 4K videos), or compute-intensive workloads (AR/VR gaming). At the heart of this processing lies the all-powerful mobile processor, which includes a multi-core CPU, GPU, memory and other IP and subsystems for performing a variety of ta... » read more

Chip Aging Becomes Design Problem


Chip aging is a growing problem at advanced nodes, but so far most design teams have not had to deal with it. That will change significantly as new reliability requirements roll out across markets such as automotive, which require a complete analysis of factors that affect aging. Understanding the underlying physics is critical, because it can lead to unexpected results and vulnerabilities. ... » read more

Disruption in High-Tech Is Here: Are You Ready?


Smart connected technology first transformed consumer electronics such as phones and tablets. Then it proliferated into cars, jets, health care, manufacturing and beyond. Today every product development team is asking “How can we incorporate smart connected technology to take our products’ performance to a new level?” Industry leaders are tackling this challenge with engineering simulatio... » read more

Blog Review: Aug. 8


Cadence's Meera Collier provides a primer on the basics of quantum computing, including how quantum gates work using superpositions and how it could impact chip design. Mentor's Dennis Brophy shares a list of resources to help you get up to speed on the recently-approved Portable Test and Stimulus standard, which enables test scenarios to be run across different execution platforms. Synop... » read more

Changing The Design Flow


Synopsys’ Michael Jackson talks with Semiconductor Engineering about why it’s becoming necessary to fuse together various pieces of digital design. https://youtu.be/AOWh4wjw-ps » read more

Auto Chip Test Getting Harder


Chipmakers and test/validation companies are helping lead the effort to develop self-driving cars, but they are facing a wide range of technical and even cultural barriers. Advanced driver assist systems (ADAS) already are the most complex systems by far in modern cars, the best of which hover between Level 2 and Level 3 on the five-step autonomy ladder maintained by the Society of Automotiv... » read more

New 5G Hurdles


Semiconductor Engineering sat down to talk about challenges and progress in 5G with Yorgos Koutsoyannopoulos, president and CEO of Helic; Mike Fitton, senior director of strategic planning and business development at Achronix; Sarah Yost, senior product marketing manager at National Instruments; and Arvind Vel, director of product management at ANSYS. What follows are excerpts of that conversat... » read more

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