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Week In Review: Auto, Security, Pervasive Computing


Automotive SGS-TÜV Saar certified that Cadence’s Tensilica Xtensa processors with FlexLock meets the ISO 26262:2018 standard to ASIL-D level. The new FlexLock feature is key to the certification because it supports lockstep, a fault-tolerant method that runs the same operation on two cores at the same time and then compares the output. Any difference in the output can be examined for issues... » read more

Blog Review: July 28


Synopsys' Chris Clark considers potential vulnerabilities in automotive over-the-air updates and best practices and new standards the industry can implement to improve security of vehicle software updates. Cadence's Paul McLellan gets a look at expected new fab construction in the coming years and where capacity is being focused. Siemens' Robin Bornoff dives into electromagnetic simulatio... » read more

Week In Review: Design, Low Power


Tools Cadence unveiled Cerebrus Intelligent Chip Explorer, a new machine learning-based tool to drive the Cadence RTL-to-signoff implementation flow. The tool aims to use reinforcement learning to find flow solutions that otherwise might not be explored and applies models to future designs. The company says it can improve productivity up to 10X and PPA up to 20% with optimization of the flow f... » read more

Blog Review: July 21


Cadence's Paul McLellan listens in as Partha Ranganathan of Google argues that a new era of Moore's Law is emerging, defined both by the efficient design of hardware accelerators and improving the ways that hardware is utilized. Siemens EDA's Chris Spear continues exploring classes in SystemVerilog with a look at the relationship between the class variables that point to an object and how to... » read more

Week In Review: Design, Low Power


Tools Andes Technology certified Imperas reference models for the complete range of Andes IP cores with the new RISC-V P SIMD/DSP extension. The reference models can be used to evaluate multicore design configuration options for SoC architecture exploration and support early software development before silicon prototypes are available. Cadence's digital full flow was optimized and certified... » read more

Week In Review: Auto, Security, Pervasive Computing


Security A new security annotation standard for hardware IP is now available for download at no cost. The board of directors of the Accellera Systems Initiative, the non-profit EDA- and IP-standards organization, approved the release of the Security Annotation for Electronic Design Integration (SA-EDI) Standard 1.0. The standard, developed by Accellera’s IP Security Assurance (IPSA) Working ... » read more

Blog Review: July 14


Siemens EDA's Wei-Lii Tan considers the tradeoffs when running library characterization in the cloud and how to think about running CPUs in parallel, the cost of throughput, and runtime reductions. A Synopsys writer checks out the reduced blanking feature in HDMI 2.1, which can help reduce the transmission rate while keeping the resolution and refresh rate intact for higher resolution displa... » read more

Chipmakers Getting Serious About Integrated Photonics


Integrating photonics into semiconductors is gaining traction, particularly in heterogeneous multi-die packages, as chipmakers search for new ways to overcome power limitations and deal with increasing volumes of data. Power has been a growing concern since the end of Dennard scaling, which happened somewhere around the 90nm node. There are more transistors per mm², and the wires are thinne... » read more

Reducing Power Delivery Overhead


The power delivery network (PDN) is a necessary overhead that typically remains in the background — until it fails. For chip design teams, the big question is how close to the edge are they willing to push it? Or put differently, is the gain worth the pain? This question is being scrutinized in very small geometry designs, where margins can make a significant difference in device performan... » read more

Lower Power Chips: What To Watch Out For


Low-power design in advanced nodes and advanced packaging is becoming a multi-faceted, multi-disciplinary challenge, where a long list of issues need to be solved both individually and in the context of other issues. With each new leading-edge process node, and with increasingly dense packaging, the potential for problematic interactions is growing. That, in turn, can lead to poor yield, cos... » read more

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