Process Variation And Aging


Semiconductor Engineering sat down to discuss design reliability and circuit aging with João Geada, chief technologist for the semiconductor business unit at ANSYS; Hany Elhak, product management director, simulation and characterization in the custom IC and PCB group at Cadence; Christoph Sohrmann, advanced physical verification at Fraunhofer EAS; and Naseer Khan, vice president of sales at M... » read more

An Integrated Simulation Platform to Validate Autonomous Vehicle Safety


Autonomous driving systems rely upon sensors and embedded software for localization, perception, motion planning and execution. Autonomous driving systems can only be released to the public after developers have demonstrated their ability to achieve extremely high levels of safety. Today’s hands-off autonomous driving systems are largely built with deep learning algorithms that can be trained... » read more

Blog Review: Jan. 16


Mentor's Harry Foster takes a look at how quickly FPGAs are adopting recent verification techniques, with formal gaining at a rapid pace. Cadence's Paul McLellan checks out the details of two new RISC-V based cores: Western Digital's open source SweRV and Esperanto's Maxion. Synopsys' Taylor Armerding digs into a recent cybersecurity report from the U.S. government and finds a troubling n... » read more

Blog Review: Jan. 9


Cadence's Paul McLellan considers the challenges facing copper interconnects as resistance gets harder to deal with and the pros and cons of potential replacement materials. Mentor's Harry Foster digs into how FPGA design and verification engineers spend their time, and why the time designers spend designing has increased. Synopsys' Taylor Armerding contends that the way we use passwords ... » read more

Blog Review: Jan. 2


Cadence's Paul McLellan listens in as Uhnder CEO Manju Hegde explains the most critical issues impacting sensor development for autonomous vehicles and why new radar systems are needed to fill in the gaps. Synopsys' Fred Bals shares key points from the U.S. House Oversight and Government Reform Committee's investigation into the massive Equifax data breach that show how relatively small secu... » read more

Week In Review: Design, Low Power


Gyrfalcon Technology released a 22nm AI accelerator ASIC chip with embedded MRAM. The Lightspeeur 2802M includes 40MB of memory to support large or multiple AI models, such as image classification and voice identification, within a single chip. Manufactured by TSMC, target applications include IoT endpoints, cloud solutions, and autonomous vehicles. Arm expanded its line of automotive-focuse... » read more

Designing For Ultra-Low-Power IoT Devices


Optimizing designs for power is becoming the top design challenge in battery-driven IoT devices, boxed in by a combination of requirements such as low cost, minimum performance and functionality, as well as the need for at least some of the circuits to be always on. Power optimization is growing even more complicated as AI inferencing moves from the data center to the edge. Even simple sens... » read more

Blog Review: Dec. 19


Cadence's Dave Pursley checks out the state of high-level synthesis and notes that 39% of survey respondents expect to be using it for the majority of designs within three years. In a video, Mentor's Colin Walls digs into how to measure RTOS performance with a focus on interrupt latency. Synopsys' Taylor Armerding chats with Chenxi Wang of Rain Capital to find what the security landscape will... » read more

Blog Review: Dec. 12


Mentor's Harry Foster checks out how much time and effort is spent on verification of FPGAs and points to the increasing demand for verification engineers. Cadence's Paul McLellan digs into IC Insights' year-end report to see how some of the top semiconductor companies stack up. Synopsys' Taylor Armerding warns that air gaps, a valuable barrier against cyberattacks, are disappearing from ... » read more

SMART Fracture


With the new unstructured mesh method (UMM) in ANSYS Mechanical, engineers can reduce preprocessing time by employing UMM’s automatically generated all-tetrahedral (tet) mesh for crack fronts, while achieving the same high-fidelity results as a simulation run with the ideal hex mesh configuration. Meshing time has been reduced from up to several days to a few minutes. Using UMM, ANSYS has ... » read more

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