tag: Mentor

Blog Review: Jan. 22
By Jesse Allen - 22 Jan, 2020 - Comments: 0

Synopsys' Taylor Armerding explains different types of social engineering scams that target everyone from CEOs to gamers to smart appliance users, and what training and tools can better protect people and their organizations. Mentor's Dennis Joseph points to some important things to consider if you're thinking about switching from GDS to OASIS and some tips for converting files. Cadence's... » read more

Three Steps To Faster Low Power Coverage Using UPF 3.0 Information Models
By Madhur Bhargava - 16 Jan, 2020 - Comments: 0

Controlling power has its costs. The added power elements and their interactions make verification of low-power designs much more difficult and the engineer’s job overwhelmingly complex and tedious. Early versions of the Unified Power Format (UPF) provided some relief, but lacked provisions for a standardized methodology for low-power coverage. Ad hoc approaches are error prone and highly ... » read more

Analog: Avoid Or Embrace?
By Brian Bailey - 16 Jan, 2020 - Comments: 0

We live in an analog world, but digital processing has proven quicker, cheaper and easier. Moving digital data around is only possible while the physics of wires can be safely abstracted away enough to provide reliable communications. As soon as a signal passes off-chip, the analog domain reasserts control for modern systems. Each of those transitions requires a data converter. The usage ... » read more

Priorities Shift In IC Design
By Ann Steffora Mutschler - 16 Jan, 2020 - Comments: 0

The rush to the edge and new applications around AI are causing a shift in design strategies toward the highest performance per watt, rather than the highest performance or lowest power. This may sound like hair-splitting, but it has set a scramble in motion around how to process more data more quickly without just relying on faster processors and accelerators. Several factors are driving th... » read more

Moore’s Law, Supply Chains And Security
By Brian Bailey - 16 Jan, 2020 - Comments: 0

The debate about the future of Moore's Law continues, while other parts of the industry look for alternatives. In between, supply chains are being pulled in multiple directions, with safety and security often in the middle. All across the semiconductor industry, significant changes are underway. Some of these have been in the works for some time. Others are new or accelerating faster than an... » read more

Random Directed Low Power Coverage Methodology
By Mentor, a Siemens Business - 15 Jan, 2020 - Comments: 0

This paper proposes a low-power coverage methodology based on the recently introduced UPF 3.0 low-power information model HDL package. Verification engineers can use this approach to achieve low-power coverage closure earlier. We share relevant case studies and examples using the methodology to solve low-power verification problems. It also discusses the benefits of this approach and its advant... » read more

Blog Review: Jan. 15
By Jesse Allen - 15 Jan, 2020 - Comments: 0

Cadence's Paul McLellan looks back at the history of lithography, from its fundamental equation to multiple patterning and the challenges facing EUV today. Synopsys' Taylor Armerding warns that medical device security isn't keeping up with new threats, despite positive steps, due in part to lack of funding, delayed initiatives, and a focus on critical service delivery. In a video, Mentor'... » read more

Improving In-System Test With Tessent VersaPoint Test Point Technology
By Mentor, a Siemens Business - 14 Jan, 2020 - Comments: 0

This paper describes a new versatile test point technology called VersaPoint, which has been developed specifically to work with designs implementing mixed EDT/LBIST methodologies to reduce EDT pattern counts and improve Logic BIST (LBIST) test coverage. VersaPoint test points can reduce compressed pattern counts 2X to 4X beyond compression alone and improve LBIST test coverage beyond what is p... » read more

Making 3D Structures And Packages More Reliable
By Ed Sperling - 14 Jan, 2020 - Comments: 0

The move to smaller vertical structures and complex packaging schemes is straining existing testing approaches, particularly in heterogeneous combinations on a single chip and in multi-die packages. The complexity of these devices has exploded with the slowdown in scaling, as chipmakers turn to architectural solutions and new transistor structures rather than just relying on shrinking featur... » read more

Planning Ahead For In-System Test Of Automotive ICs
By Jeff Mayer - 14 Jan, 2020 - Comments: 0

Automobiles are increasingly more like electronic devices than mechanical platforms. As a share of the total cost of a car, electronics components have grown from about 5% in 1970 to 35% in 2010. Electronics are projected to account for 50% by 2030 (Deloitte, 2019). Some of the electronics are for passive operations, like display or In-Vehicle Infotainment (IVI) systems, but a growing proportio... » read more

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