tag: Mentor

Week In Review: Design, Low Power
By Jesse Allen - 21 Sep, 2018 - Comments: 0

Tools & IP Cadence unveiled deep neural-network accelerator (DNA) AI processor IP, Tensilica DNA 100, targeted at on-device neural network inference applications. The processor is scalable from 0.5 TMAC (Tera multiply-accumulate) to 12 TMACs, or 100s of TMACs with multiple processors stacked, and the company claims it delivers up to 4.7X better performance and up to 2.3X more performance p... » read more

Auto Chip Design, Test Changes Ahead
By Kevin Fogarty - 19 Sep, 2018 - Comments: 0

The automotive industry’s unceasing demand for performance, coupled with larger and more complex processors, are driving broad changes in how electronics are designed, verified and tested. What's changing is that these systems, which include AI-oriented logic developed at the most advanced process nodes, need to last several times longer than traditional IT and consumer devices, and they n... » read more

Blog Review: Sept. 19
By Jesse Allen - 19 Sep, 2018 - Comments: 0

Applied Materials' David Thompson shares the new DARPA program that is focused on using correlated electrons to develop a new type of switch with quantum effects, potentially leading to unprecedented switching speeds. Mentor's Joe Hupcey III argues that for the most effective formal analysis, assertions should be as simple as possible and shares some tips on decomposing big assertions. Ca... » read more

Aging In Advanced Nodes
By Ann Steffora Mutschler - 17 Sep, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss design reliability and circuit aging with João Geada, chief technologist for the semiconductor business unit at ANSYS; Hany Elhak, product management director, simulation and characterization in the custom IC and PCB group at Cadence; Christoph Sohrmann, advanced physical verification at Fraunhofer EAS; Magdy Abadir, vice president of marketing at ... » read more

Week In Review: Design, Low Power
By Jesse Allen - 14 Sep, 2018 - Comments: 0

M&A Intel acquired NetSpeed Systems, a network-on-a-chip and interconnect fabric IP and tool provider. Founded in 2011, the San Jose-based company recently put a focus on interconnects designed with AI applications in mind. Intel has cast the acquisition as a way to tie a number of its other technologies together. The team will join Intel's Silicon Engineering Group. Intel has been a NetSp... » read more

Week in Review: IoT, Security, Auto
By Jeff Dorsch - 14 Sep, 2018 - Comments: 0

Internet of Things NXP Semiconductors provided its A71CH trust anchor to Google IoT Cloud, enabling authentication for Google IoT Cloud Core. The technology helps to secure edge devices for Internet of Things deployments. Separately, NXP announced the promotion of Kurt Sievers, executive vice president and general manager of the chip company’s automotive business, to president of NXP Semicon... » read more

Solving Puzzling Power-Aware Coverage: Getting An Aggregated Coverage Metric
By Progyna Khondkar - 13 Sep, 2018 - Comments: 0

Coverage metrics tell us when a design has been thoroughly verified, or at least exercised to the point of diminishing returns. Rarely can every design artifact or design parameter of a highly complex design be covered 100 percent, but we can use coverage metrics to know the extent to which we have verified the design — enough to be confident that it will function as desired in the end produc... » read more

Enabling Cheaper Design
By Brian Bailey - 13 Sep, 2018 - Comments: 1

While the EDA industry tends to focus on cutting edge designs, where design costs are a minor portion of the total cost of product, the electronics industry has a very long tail. The further along the tail you go, the more significant design costs become as a percent of total cost. Many of those designs are traditionally built using standard parts, such as microcontrollers, but as additional... » read more

Process Corner Explosion
By Ann Steffora Mutschler - 13 Sep, 2018 - Comments: 1

The number of corners that need to be checked is exploding at 7nm and below, fueled by everything from temperature and voltage to changes in metal. Lowering risk and increasing predictability of an SoC at those nodes starts with understanding what will happen when a design is manufactured on a particular foundry process, captured in process corners. This is basically a way of modeling what i... » read more

Minimizing Chip Aging Effects
By Brian Bailey - 13 Sep, 2018 - Comments: 2

Aging kills semiconductors, and it is a growing problem for an increasing number of semiconductor applications—especially as they migrate to more advanced nodes. Additional analysis and prevention methods are becoming necessary for safety critical applications. While some aspects of aging can be mitigated up front, others are tied to the operation of the device. What can an engineering tea... » read more

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