tag: Mentor

Here At Last! Automated Verification Of Heterogeneous 2D/3D Package Connectivity
By Michael Walsh - 25 Jul, 2024 - Comments: 0

By Michael Walsh and Jin Hou with Todd Burkholder The heterogeneous integration of multiple ICs in a single package along with high-performance, high-bandwidth memory is critical for many high-performance computing applications. After everything has been heterogeneously integrated and packaged, such designs feature complex connectivity with many hundreds of thousands of connections, making i... » read more

Floor-Planning Evolves Into The Chiplet Era
By Karen Heyman - 25 Jul, 2024 - Comments: 0

3D-ICs and heterogeneous chiplets will require significant changes in physical layout tools, where the placement of chiplets and routing of signals can have a big impact on overall system performance and reliability. EDA vendors are well aware of the issues and working on solutions. Top on the list of challenges for 3D-ICs is thermal dissipation. Logic typically generates the most heat, and ... » read more

What’s Next In System-Level Design?
By Ann Mutschler - 25 Jul, 2024 - Comments: 0

Experts At The Table: EDA has undergone numerous workflow changes over time. Different skill sets have come into play over the years, and at times this changed the definition of what it means to design at the system level. Semiconductor Engineering sat down to discuss what this means for designers today, and what the impact will be in the future, with Michal Siwinski, chief marketing officer at... » read more

Heat-Related Issues Impact Reliability In Advanced IC Designs
By Ann Mutschler - 18 Jul, 2024 - Comments: 1

Heat is becoming a much bigger problem in advanced-node chips and packages, causing critical electrons to leak out of DRAM, timing and reliability issues in 3D-ICs, and accelerated aging that are unique to different workloads. All types of circuitry are vulnerable to thermal effects. It can slow the movement of the electrons through wires, cause electromigration that shortens the lifespan of... » read more

A Guide To Rigid-Flex PCB Design
By Gregory Beers - 18 Jul, 2024 - Comments: 0

In today’s electronics industry, compact, efficient, and versatile PCBs are in high demand. Rigid-flex technology allows engineers to design boards that bend and flex without compromising performance or reliability. Mastering rigid-flex PCB design can be challenging due to its unique requirements. Whether you're an experienced designer expanding your skills or new to the field, this ar... » read more

Data Center Thermal Management Improves
By Karen Heyman - 18 Jul, 2024 - Comments: 0

Thermal issues are plaguing semiconductor design at every level, from chips developed with single-digit nanometer processes to 100,000-square-foot data centers. The underlying cause is too many devices or services that require increasing amounts of power, and too few opportunities for the resulting heat to dissipate. “Everybody wants to try to do more in a small volume of space,” said St... » read more

IC Power Optimization Required, But More Difficult To Achieve
By Adam Kovac - 18 Jul, 2024 - Comments: 0

Power optimization is playing an increasingly vital role in chip and chip and system designs, but it's also becoming much harder to achieve as transistor density and system complexity continue to grow. This is especially evident with advanced packages, chiplets, and high-performance chips, all of which are becoming more common in complex designs. Inside data centers, racks of servers are str... » read more

Rigid-Flex PCB Design Guidelines
By Siemens EDA - 17 Jul, 2024 - Comments: 0

This white paper is designed to guide you through the intricacies of rigid-flex printed circuit board (PCB) design. In today's electronics industry, there has never been more demand for compact, efficient, and versatile PCBs. Rigid-flex technology has emerged as a game-changer, offering engineers the flexibility to design boards that can bend and flex without sacrificing performance or reliabil... » read more

Blog Review: July 17
By Jesse Allen - 17 Jul, 2024 - Comments: 0

Cadence's Xin Mu explains the PCIe ECN Unordered IO (UIO) feature in the PCIe 6.1 specification, which defines a new wire semantic and related capabilities to enable multiple-path fabric support and helps avoid unnecessary traffic for better bandwidth and latency. Synopsys' Dana Neustadter, Gary Ruggles, and Richard Solomon highlight the latest updates in the CXL 3.1 standard, including new ... » read more

Managing kW Power Budgets
By Ed Sperling - 17 Jul, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss increasing power demands and how to address it with Hans Yeager, senior principal engineer, architecture, at Tenstorrent; Joe Davis, senior director for Calibre interfaces and EM/IR product management at Siemens EDA; Mo Faisal, CEO of Movellus; Trey Roessig, CTO and senior vice president of engineering at Empower Semiconductor.... » read more

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