Getting power into and around a chip is becoming a lot more difficult due to increasing power density, but 2.5D and 3D integration are pushing those problems to whole new levels.
The problems may even be worse with new packaging approaches, such as chiplets, because they constrain how problems can be analyzed and solved. Add to that list issues around new fabrication technologies and an emph... » read more
Optimizing performance, power and reliability in consumer electronics is an engineering feat that involves a series of tradeoffs based on gathering as much data about the use cases in which a design will operate.
Approaches vary widely by market, by domain expertise, and by the established methodologies and perspective of the design teams. As a result, one team may opt for a leading-edge des... » read more
By Allan Crone
A predictable trend in IC design is the ever-increasing size and complexity of designs while keeping the time allocated for the projects the same or shorter. Along with the tape-out pressure, organizations need to find cost savings everywhere possible. Lowering the overall cost of ownership of EDA tools is a viable way to manage the design budget. Consequently, design teams ar... » read more
This paper uses examples and case studies to demonstrate how to leverage UPF 3.0 information model TCL query functions (aka Tcl Apps) and tool provided CLI commands to do low-power checking of a design. This is an innovative way to dynamically verify the low-power intent after simulation has completed and all waveforms are available. The paper also explains how users can write their own checker... » read more
Cadence's Paul McLellan checks out the challenges of processing-in-memory and the steps involved in building a logic flow on a DRAM process.
Synopsys' Taylor Armerding notes that with safety-critical software an ever-present factor in modern life, it's more necessary than ever to take the time to ensure quality and security when failures can be life-threatening.
In a video, Mentor's Colin... » read more
Semiconductor testing is getting more complicated, more time-consuming, and increasingly it requires new approaches that have not been fully proven because the technologies they are addressing are so new.
Several significant shifts are underway that make achieving full test coverage much more difficult and confidence in the outcome less certain. Among them:
Devices are more connected an... » read more
Charged with the task of improving yield, product engineers need to find the location of defects in manufactured ICs quickly and efficiently. Typically, they use volume scan diagnosis to generate large amounts of data from failing test cycles, which is then analyzed to reveal the location of defects. Scan failure data provides the basis for many decisions in the failure analysis and yield impro... » read more
Performing volume scan diagnosis on today’s large, advanced node designs puts demands on turn-around-time and compute resources. This paper describes a new technique to maximize diagnosis throughput while performing ever more demanding scan diagnosis. The dynamic partitioning technology in Tessent Diagnosis enables in a 50% reduction in scan diagnosis time using only 20% of the typical memory... » read more
Ron Squiers, network solutions specialist at Mentor, a Siemens Business, explains what’s different in 5G chips versus 4G, how to construct a front haul and back haul system so it is testable in the network stack.
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Rambus will acquire the Silicon IP, Secure Protocols and Provisioning business from Verimatrix, formerly Inside Secure. The secure silicon IP and provisioning solutions from both companies will be integrated into a single portfolio of products and the embedded security teams from Verimatrix will join Rambus. “Integrating the Verimatrix embedded security team into Rambus, a recognized leader i... » read more
