Safety Plus Security: Solutions And Methodologies


By Ed Sperling & Brian Bailey As more technology makes its way into safety-critical markets—and as more of those devices are connected to the Internet—security issues are beginning to merge with safety issues. The number of attempted cyberattacks is up on every front, which has big implications for devices used in safety-related applications. There are more viruses, ransomware, an... » read more

Wednesday At DAC


Wednesday at DAC started off in usual fashion with a keynote. For the third day, the focus of the talk was the IoT and how significant the change is going to be. Tyson Tuttle, CEO of Silicon Labs, was the speaker. While there are a lot of figures about how many devices will be connected in the future, Tuttle put it into a different perspective. "There will 70B connected devices by 2025 worth $... » read more

Verification Unification


Semiconductor Engineering brought together industry luminaries to initiate the discussion about the role that formal technologies will play with Portable Stimulus and how it may help to bring the two execution technologies closer together. Participating in this roundtable are Joe Hupcey, verification product technologist for [getentity id="22017" e_name="Mentor, a Siemens Business"]; Tom Fitzpa... » read more

Tuesday At DAC


Accellera got everyone out of bed early this morning to talk about the just announced early access release of Portable Stimulus. The panel was made up with people from user companies. Semiconductor Engineering will be providing full coverage of this event, but perhaps the important message is that the panelists were eager to get adoption within their companies but knew that there would be chall... » read more

Blog Review: June 21


Mentor's John McMillan looks into the unique form-factors and components influencing IoT PCB designs. Cadence's Paul McLellan notes some big topics at the Samsung Foundry Forum: FD-SOI, embedded MRAM, and which gate-all-around FET architecture may be the winner. Synopsys' Eric Huang has a lighthearted look at why to buy IP versus building it. Rambus' Aharon Etengoff points to another U... » read more

Monday At DAC


The 54th DAC got started today in a very steamy Austin. While we may be a maturing industry, there is certainly no indications that the people within the industry have given up or intend to take it easy. The event really got started late Sunday when Laurie Balch, chief analyst for Gary Smith EDA, delivered her message. She said that the focus is becoming the verticals. "This change in focus is ... » read more

The Week In Review: Design


M&A Verific acquired Invionics' entire INVIO technology portfolio, adding a high-level scripting interface with 100 high-level APIs to its Parser Platform of approximately 2,000 low-level SystemVerilog and VHDL APIs. An R&D group from the company will also join Verific. Portable Stimulus An Early Adopter release of the Portable Stimulus specification has been made publicly availabl... » read more

Modeling On-Chip Variation At 10/7nm


Simulation, a workhorse tool for semiconductor design, is running out of steam at 10/7nm. It is falling behind on chips with huge gate counts and an enormous number of possible interactions between all the different functions that are being crammed onto a die. At simulation's root is some form of SPICE, which has served as its underpinnings ever since SPICE was first published 44 years ago. ... » read more

Blog Review: June 14


In a video, Cadence's Tom Hackett looks at the evolving von Neumann computer architecture and the development of CCIX driven by recent cloud computing challenges. Mentor's Puneet Sinha notes it's been 17 years since the Toyota Prius went on sale worldwide, and looks ahead to the next 17 years of electric vehicles. Synopsys' Sri Deepti Pisipati gives an overview of the different topologies... » read more

The Week In Review: Design


Tools Mentor added new tools to its high-level synthesis portfolio. The DesignChecks tool helps find bugs during coding with a static mode that performs very fast linting-like checks of the code and a formal mode that uses a formal engine for a more exhaustive proof of issues. The synthesis-aware Coverage tool measures code coverage for C++ signoff and fast closure of synthesized RTL. It sup... » read more

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