tag: Mentor

Addressing Silicon Lifecycle Scaling Demands
By Marc Hutner - 10 Jul, 2025 - Comments: 0

In today’s competitive business landscape, navigating complexity can be a decisive advantage, but it also presents significant challenges. Three crucial trends driving the rise of complexity are technology scaling, design scaling and system scaling. Traditionally, Design for Test (DFT) solutions have focused on the die level; however, these challenges present opportunities at the package and ... » read more

Easing The Stress For Package-Level Burn-In
By Laura Peters - 10 Jul, 2025 - Comments: 0

Considered something of a necessary evil, burn-in of IC packages during production weeds out latent defects so they don’t turn into failures in the field. But as AI and multi-chiplet packages become more common, and concerns about aging circuitry heighten, shifting stress testing to the wafer level looks increasingly attractive from a quality, throughput, and cost standpoint. The shift is ... » read more

Using High-Quality Deterministic Patterns For In-System/In-Field Testing
By Siemens EDA - 10 Jul, 2025 - Comments: 0

Logic BIST (LBIST) is a well-stablished traditional solution for meeting automotive testing standards. However, using pseudo-random LBIST patterns can be challenging when trying to achieve high-quality testing due to the increased complexity of designs. The growing amount of electronic content, along with the shift toward fully autonomous vehicles, demands stringent testing requirements. In-... » read more

AI Pushes High-End Mobile From SoCs To Multi-Die
By Liz Allan - 08 Jul, 2025 - Comments: 0

Advanced packaging is becoming a key differentiator for the high end of the mobile phone market, enabling higher performance, more flexibility, and faster time to market than systems on chip. Monolithic SoCs likely will remain the technology of choice for low-end and midrange mobile devices because of their form factor, proven record, and lower cost. But multi-die assemblies provide more fle... » read more

3D-IC Stress Analysis
By Shetha Nolke - 08 Jul, 2025 - Comments: 0

The semiconductor industry is undergoing a transformation as 3D integrated circuits (ICs) and heterogeneous packaging become mainstream. With these advances comes the promise of higher functional density, a smaller footprint and enhanced system performance. However, these same innovations introduce new mechanical stressors within complex assemblies, posing novel reliability risks across the dev... » read more

AI: A New Tool For Hackers, And For Preventing Attacks
By Ann Mutschler - 08 Jul, 2025 - Comments: 0

Semiconductor Engineering sat down to discuss hardware security challenges, including new threat models from AI-based attacks, with Nicole Fern, principal security analyst at Keysight; Serge Leef, AI-For-Silicon strategist at Microsoft; Scott Best, senior director for silicon security products at Rambus; Lee Harrison, director of Tessent Automotive IC Solutions at Siemens EDA; Mohit Arora, seni... » read more

6G Rollout Will Be A Patchwork At First
By Liz Allan - 08 Jul, 2025 - Comments: 0

6G is expected to begin rolling out in 2030, but advances in 5G will inch cellular technology close enough that it will make the first 6G implementations seem more like just another upgrade. That's just the starting point, though. 6G technology gets much more interesting from there, connecting more devices at a significantly higher data rate, and enabling services that would be unattractive to ... » read more

Chip Industry Week in Review
By The SE Staff - 03 Jul, 2025 - Comments: 0

[Editor's Note: Early edition due to the U.S. July 4th holiday.] The U.S. government lifted export restrictions that barred Synopsys, Siemens EDA, and Cadence from selling EDA tools to China. In a statement, Synopsys said it received a letter from the U.S. Commerce Department immediately rescinding those restrictions. Siemens issued a similar statement. Which tools or hardware accelerated t... » read more

Rethinking Scan Chains In Semiconductor Test
By Ed Sperling - 02 Jul, 2025 - Comments: 0

An explosion in design complexity, fueled by increased transistor density and fundamental shifts in chip architectures, are beginning to overwhelm traditional approaches to test. Defects can show up in the clock trees that drive scan chains, and even inside blocks of scan cells, which may number in the millions. Jayant D'Souza, technical product director for yield learning products in Siemens E... » read more

Blog Review: July 2
By Jesse Allen - 02 Jul, 2025 - Comments: 0

Synopsys’ Shankar Krishnamoorthy chats with industry experts about how the combination of AI and software-defined systems is driving a re-evaluation of engineering workflows and why chip, software, and system development must evolve in unison. Siemens’ Jake Wiltgen considers the rapidly evolving and growing challenge of performing DFT verification as designs scale, with complex hierarchi... » read more

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