200mm Fab Crunch


Growing demand for analog, MEMS and RF chips continues to cause acute shortages for both 200mm fab capacity and equipment, and it shows no sign of letting up. Today, 200mm fab capacity is tight with a similar situation projected for the second half of 2018 and perhaps well into 2019. In fact, 2018 will likely represent the third consecutive year that 200mm fab capacity will be tight. The sam... » read more

The Power Of De-Integration


The idea that more functionality can be added into a single chip, or even into a single system, is falling out of vogue. For an increasing number of applications, it's no longer considered the best option for boosting performance or lowering power, and it costs too much. Hooman Moshar, vice president of engineering at Broadcom, said in a keynote speech at Mentor's User2User conference this w... » read more

What’s Missing In EUV?


Extreme ultraviolet (EUV) lithography is expected to move into production at 7nm and/or 5nm, but as previously reported, there are some gaps in the arena. At one time, the power source was the big problem, but that appears to be solved in the near term. Now, a phenomenon called stochastic effects, or random variations, are the biggest challenge for EUV lithography. But at most events, th... » read more

RF SOI Wars Begin


Several foundries are expanding their fab capacities for RF SOI processes amid huge demand and shortages of this technology for smartphones. A number of foundries are increasing their 200mm RF SOI fab capacities to meet soaring demand. Then, GlobalFoundries, TowerJazz, TSMC and UMC are expanding or bringing up RF SOI processes in 300mm fabs in an apparent race to garner the first wave of RF ... » read more

Blog Review: May 9


Mentor's Doug Amos explains the differences (and similarities) between verification and validation, why switching between engines needs to be simpler, and why the limits of verification are driving a growth in validation importance. Synopsys' Melissa Kirschner provides a primer on 5G and the five technologies that will need to work in tandem to bring the promised high speeds and low latency.... » read more

The Case For Chiplets


Discussion about chiplets is growing as the cost of developing chips at 10/7nm and beyond passes well beyond the capabilities of many chipmakers. Estimates for developing 5nm chips (the equivalent 3nm for TSMC and Samsung) are well into the hundreds of millions of dollars just for the NRE costs alone. Masks costs will be in the double-digit millions of dollars even with EUV. And that's assum... » read more

The Week In Review: Manufacturing


Chipmakers Consumers recently filed a class-action suit against the three DRAM makers, alleging that they illegally agreed to raise prices for their respective memory products. The suit, filed in the U.S. District Court for the Northern District of California, alleges that Samsung, Micron and Hynix agreed to limit the supply of DRAM, driving up prices for this widely used memory. The pr... » read more

The Week In Review: Design


M&A ANSYS finalized its acquisition of OPTIS. Founded in 1989, OPTIS provided software for scientific simulation of light, human vision and physics-based visualization. The acquisition boosts the company's automotive simulation portfolio with radar, lidar and camera simulation. Terms were not disclosed. IP Arm debuted the Cortex-M35P processor. Aimed at IoT applications, the IP combine... » read more

Timing Signoff Methodology For eFPGA


An eFPGA is a hard IP block in an SoC. Most SoCs are made up of a collection of hard IP blocks (RAM, SerDes, PHYs…) and the remaining logic is constructed using Standard Cells. The timing signoff for an eFPGA’s interface with the rest of the chip is designed to leverage standard ASIC timing signoff flow for a hard-macro: as long as inputs/output to/from the eFPGA are all flopped, the int... » read more

Tech Talk: eFPGA Timing


Flex Logix's Chen Wang talks about timing for an embedded FPGA and how that differs from ASIC timing. https://youtu.be/n88D1N4IEbs » read more

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