Backside Power Delivery Gears Up For 2nm Devices

But this novel approach to optimizing logic performance depends on advancing lithography, etching, polishing, and bonding processes.


The top three foundries plan to implement backside power delivery as soon as the 2nm node, setting the stage for faster and more efficient switching in chips, reduced routing congestion, and lower noise across multiple metal layers.

The benefits of using this approach are significant. By delivering power using slightly fatter, less resistive lines on the backside, rather than inefficient frontside approaches, power losses can be reduced by 30% due to less voltage drop. In a typical advanced-node processor, power lines may traverse 15 or more layers of interconnect. The change also frees up routing resources on the frontside for signals, especially at the first and most costly metal layer, and it reduces various types of interactions that have vastly increased design complexity due to sometimes unpredictable, workload-dependent physical effects.

Intel likely will be the first to adopt backside power delivery, as it races to regain its process technology leadership, but Samsung and TSMC will follow soon afterward.

Fig. 1: Backside power delivery reduces voltage droop and RC delays but takes longer to fully process. Source: Intel

This is not a simple change, however. Backside power delivery (BPD) introduces a slew of processing challenges, including lithography corrections for distortions due to extreme wafer thinning and bonding of wafer backside to frontside, the latter of which contain millions of nanoTSVs per chip.

Nonetheless, backside power delivery appears to be worth the effort. “There was a lot of learning that helped us to pave the path for this process. For instance, optimizing how you grind the wafer down precisely so that you don’t damage the transistor itself,” said Ben Sell, vice president of technology development at Intel.

Sell’s group is optimizing the PowerVia using the Intel 4 process and finFET transistors, with first devices revealed at the VLSI Symposium last year. [1] The company plans to combine PowerVia with its RibbonFET (gate all around) transistors at the 20A node (2nm). With BPD, the device was able to achieve a 6% performance boost (Fmax), 90% cell utilization and >30% lower voltage droop. “Now that you have routing on both sides, it really helps us to pack standard cells closer together,” said Sell. “We call this utilization, in terms of how much of the area you’re actually utilizing with the cells.”

Fig. 2: Wafer backside used 4 levels of interconnect while the frontside used 14 levels, connecting µvias to the contact level. Source: Intel

Samsung is developing backside power delivery, as well, and early studies indicate it will achieve impressive performance metrics. [2] Using two different Arm cores, the company reported a frequency improvement of 3.6%, and area reductions of 10% and 19%. Power and ground delivery takes place using ‘power-tap’ cells between the standard cells. The team also expects a reduction in standard cell block area.

Superior routing efficiency
The ideal power delivery network enables constant, stable supply of current to active circuits on the IC during any activity. One of the most important parameters is the DC resistance of the PDN in all interconnect paths, from the power supply pins of the IC to the transistors in the circuits.

Fig. 3: Backside power delivery dramatically shortens the path between bumps and the transistors versus having to traverse 15 or more interconnect layers on the frontside, which suffer from high voltage loss. Source: Applied Materials

IR drop is the bottleneck in highly scaled interconnects. By going to backside power delivery, designers can independently optimize routing with fatter copper lines for power and ground on the backside and thinner copper on the frontside to carry signals. Device manufacturers remove the power grid from the costly, metal-0 level, which requires double patterning or even triple patterning using EUV. With BPD, that layer loosens metal-0 pitch from 30nm to 36nm. According to Sell, that change alone more than pays for the additional process layers, even though throughput is longer. The relieved congestion also reduces RC delay so transistors can operate at higher frequency. “Much of the cost benefit came from using a simpler EUV flow that requires a lot less tooling. Maybe you can do that lithography with a single pass rather than having two or three passes.”

Backside power deliver, which was proposed by imec researchers in 2019, is a key step toward continued logic scaling. There are three main categories for this approach (see figure 4, below).

Fig. 4: BPD schemes afford different levels of scaling benefits associated with increasing levels of wafer processing complexity. Source: Applied Materials

The simplest approach connects a deep via from the power rail around the CMOS FETs up to the first metal and down through the top contact. PowerVia uses nanoTSVs to connect the backside power network to the contact level of the transistor, enabling superior scaling. Finally, the ‘direct connect’ approach directly links backside microvias to each transistor’s source and drain region.

Direct connect enables the best scaling, but it’s the riskiest of the three. “Here you put metal between the fins before you make the devices,” said Eric Beyne, senior fellow, vice president of R&D and program director 3D System Integration at imec. “It is a bit scary for people to do metal processing before the front end, but that allows you to make contacts and have a bit more space. The problem is that you need to align the photolithography on the backside to the frontside, but this wafer has been bonded and thinned so you get distortion.”

Unfortunately, top wafer distortions exist alongside the need to align features on top and bottom wafers. Even with aligned wafers in the bonding, adaptive lithography schemes on the scanner are needed to enable the corrections, and the corrections are complex. Not all are transferred in the same direction. Meanwhile, overlay budgets are shrinking. Beyne estimates that, depending on the scheme, there may be 10 to 20nm overlay to work with. That drops precipitously to 3nm for more direct connect approaches, which likely will require even more control over bonding-induced distortion.

“These are tiny source/drain features, because the CPP (contacted gate pitch) is only 45nm,” said Beyne. “So landing on S/D is quite challenging, and must be extremely accurate.”

The microvias tend to be around 10:1 aspect ratio (height/width). Precisely controlled etching processes are essential for new µvias, as well as for other critical features. “All three approaches to BPD involve high-aspect-ratio features that need to be etched and then filled with a conductor, an insulator, or both,” said Kaihan Ashtiani, corporate vice president and general manager at Lam Research.

The wafer thinning process itself is not all that straightforward, either. Only around 500nm of silicon remains after thinning. Imec is working with engineers at Disco to improve the uniformity and processing speed of the grinding process.

CMP plays a critical too. David Kretz, senior director at Lam Research, explained that the course grinding process is followed by a fine polish (CMP) to land close to the final target thickness and fully remove grinding damage. Then wet cleaning or dry etch removes the remaining silicon. Silicon germanium (SiGe) can act as etch stop.

“Wet silicon etching was first developed for CMOS imaging and power devices. Additional applications were developed for wafer bonding, particularly for NAND devices — bonding the CMOS array to the memory cells,” said Kretz. Such etching techniques are now being applied in backside power rail applications.

Wet challenges include cost effectiveness, uniformity (total thickness variation, TTV), and repairing silicon damage from the grinding step. “Lam overcomes these challenges by using a fast etch-rate process first to remove the bulk silicon (cost effectiveness), and then switching to a lower etch-rate process that enables us to better control the final film roughness,” said Kretz.

Metrology plays an essential role in monitoring uniformity. “Our Integrated Thickness Measurement System (ITMS) enables customers to measure the wafer before wet etch so we can adjust our process for incoming thickness variations from the grind process,” he explained. “This results in an overall tighter control of the final wafer-to-wafer thickness variation.”

Fig. 5: The transistors and power via are fabricated first (a), followed by multi-level frontside metallization and dielectric seal (b), bonding to silicon carrier (c), then backside power processing. Source: Intel

In Intel’s simplified process flow (see figure 5), the process first builds the finFET or gate-all-around transistors, and then nanovias are etched and filled with tungsten or other low-resistance metal. Next, the signal interconnects (M0 to M14) are fabricated using slightly larger metal-0 lines than would be needed with a frontside power distribution network. Next, a dielectric (hermetic) seal is deposited, followed by flipping the front-end wafer and mounting it on a carrier wafer. Then, the silicon is ground and polished (CMP). An etch stop helps prevent removal of the transistors themselves.

The most challenging and complex flow, direct contact, contacts metal to the sources and drains of the transistors. “In the direct source contact approach, aligning between frontside and backside connections is a challenge. Further, epi contact formation is done from the frontside, leaving a backside overhang. Since metal fill is done from the backside, metallization of the overhang structure is an added challenge,” said Ashtiani.

Ashtiani elaborated on the thermal budget restrictions due to the presence of an already built copper stack, which is causing engineers to actively evaluate metal alternatives such as ruthenium and molybdenum. “Molybdenum is emerging as a compelling alternative to replace tungsten for advanced chipmaking,” he said. “Epi backside contact is fabricated after BEOL process, and is thus subject to a temperature ceiling of 400 to 450°C. Formation of an ohmic, low-resistance contact within the BEOL thermal budget will be a big challenge.”

In Lam’s work, molybdenum deposition has shown the ability to form ohmic contacts, using low-temperature atomic layer deposition (ALD) of molybdenum in conformal and bottom-up contact fill schemes. Other advantages of molybdenum include a shorter mean free path. With that, resistivity remains lower even at smaller feature sizes. Moreover, it has no intrinsic diffusivity into dielectrics, so a higher-resistivity barrier is not needed.

Another metal being tested is ruthenium. In multiple studies, ruthenium has been explored as an alternative contact material for front-end contacts, and imec showed that ruthenium in backside power delivery can lower resistance by 40% relative to tungsten power rails. The key difference between the two metals is one of cost. Ruthenium precursors are an order of magnitude more expensive than molybdenum precursors.

Fault isolation and debug traditionally are performed through the silicon backside when all the interconnects are confined to the wafer frontside. That analysis changes with backside metallization. “When you have metal on both sides, obviously it’s harder because all of a sudden you have metal layers in the way. There are different techniques that we had to develop to make sure we can still localize defects and characterize them even through these metal lines,” said Intel’s Sell. The company is using both existing and novel debug techniques to perform these analyses.

Testing, meanwhile, is performed to identify speed path issues using at-speed scan test patterns to identify and fix the performance-limiting paths in the design so devices can run at higher clock frequencies. For each failing scan cell, the failing paths are identified based on structural analysis of logic simulation values.

Yield and reliability
To ensure reliability, chipmakers employ the same reliability testing methods that would be used for any complex logic device, including time dependent dielectric breakdown (TDDB), bias temperature instability (BTI), hot carrier injection (HCI).

Interestingly, Samsung analyzed the thermo-mechanical reliability associated with the packaging process to ensure no discontinuities. The engineers analyzed the stress levels induced by the multi-layer metal stack, including backside power delivery versus the stresses induced with a traditional interconnect stack. The team used modeling to compare the scenarios at its 4nm node with flip-chip packaging. “…We select the location at the highest tensile stress exerted in the single bump, which is the bump located at the edge of the chip, and examine the BEOL sub-model under thermal displacement boundary conditions from package model,” they said in a recent article.

The chip with backside power exerted 62% greater tensile stress in the z-direction, which concentrated at the first metal layer just above the nanoTSV. The team took measurements, including nanoTSV dimensional adjustments. By making the TSVs 10% wider (or shorter), the stress was relieved and resistance lowered, also delivering speed improvements using ring oscillator simulations. They showed both the dimensions of the TSVs and the barrier metal thickness influence stress and performance.

Stress buildup in general is an increasing concern in the industry, especially with more and more use of temporary bonding processes so that different architectures or materials can be combined. “Customers expect a bonding material that will hold the device wafer to a carrier through the entire process without delamination,” said Rama Puligadda, CTO of Brewer Science. “So the release layer cannot release the bond until everything is done and truly ready for debonding. But then it needs to release very easily, either by mechanical means or using a laser. So that balance is more challenging with an extremely stressed wafer.”

Backside power delivery is a breakthrough approach that more efficiently delivers power to devices, while also improving the manufacturability of the smallest front-end interconnects. The process improvements are happening around lithography corrections for distortion, CMP, etching, cleaning, and bonding processes. Isolating faults has gotten more challenging. Nevertheless, this approach to producing faster logic devices is expected to show up in devices as early as next year.

1. W. Hafez et al., “Intel PowerVia Technology: Backside Power Delivery for High Density and High-Performance Computing,” 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, 2023, pp. 1-2, doi: 10.23919/VLSITechnologyandCir57934.2023.10185208.
2. S. Kim et al., “Structural Reliability and Performance Analysis of Backside PDN,” 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, 2023, pp. 1-2, doi: 10.23919/VLSITechnologyandCir57934.2023.10185330.

Related stories

Challenges In Backside Power Delivery

Big Changes Ahead In Power Delivery, Materials, And Interconnects

How Far Will Copper Interconnects Scale?


Allen Rasafar says:

Thank you for sharing this insight to 2nm technology node.

Leave a Reply

(Note: This name will be displayed publicly)