How Far Will Copper Interconnects Scale?

Creative methods keep extending the performance of copper lines and vias.


As leading chipmakers continue to scale finFETs — and soon nanosheet transistors — to ever-tighter pitches, the smallest metal lines eventually will become untenable using copper with its liner and barrier metals. What comes next, and when, is still to be determined. There are multiple options being explored, each with its own set of tradeoffs.

Ever since IBM introduced the industry to copper interconnects with dual damascene processing in the 1990s, the semiconductor industry has been taking advantage of copper’s high conductivity, low resistivity, and reliable interconnection. But as both resistance and capacitance rise, RC delay will continue to significantly impact device performance.

Alternatives to copper, like ruthenium and molybdenum, can be integrated using dual damascene. Still, they may be better suited to subtractive schemes with metal etch, which hasn’t been widely used in logic since the aluminum interconnect days. Nonetheless several interesting avenues are being pursued for these lowest levels of copper by leading device makers and equipment companies alike. In parallel, engineers and research teams are extending copper further, which offers the more affordable and attractive route by far.

“Dual damascene has been, and is still, the bread and butter of the interconnect for the last 25 years. But we see that for reasons of RC delay, metal patterning could become relevant,” said Zsolt Tokei, imec fellow and program director of nano-interconnects. Imec’s scheme is called semi-damascene, and because the transition to subtractive processes will be dramatic, it may be introduced gradually. “We think that at first it will be used for one layer, but later on this will propagate to several layers. This is combined with self-aligned vias, and perhaps changes to the middle of line, as well.”

At the same time, system performance drivers are making it attractive to move memory devices into the backend of line, if possible. If and when the industry begins to introduce interconnect processes with lower thermal budgets, things like memory or other device integration become feasible. But first, the immediate engineering challenges of extending copper and introducing backside power distribution schemes must be settled.

More mileage from copper
At the 2nm logic node, copper lines and vias are being extended through creative means. Some of the most attractive options involve limiting the resistivity impact from barrier and liner materials, either by making these films thinner — going from chemical vapor deposition (CVD) to atomic layer deposition (ALD) — or eliminating them, for instance, along the vertical path between vias and lines.

Both TEL and Applied Materials offer integrated processes using self-assembled monolayers (SAMs) to achieve selective deposition. These SAMs, which use either CVD or spin-on films, selectively deposit typically on metal, but not dielectric, so that cobalt or ruthenium liners, or barriers such as ALD Ta/TaN, adhere to the desired surfaces.

In a presentation at IITC, Yuki Kikuchi and colleagues in TEL‘s Corporate R&D Department, and JSR Micro, showed improvements in resistance and copper volume associated with using JSR’s SAM to inhibit ALD TaN, and even replace the copper barrier metal. [1] The best selectivity to low-k dielectric (2.5) was achieved by using one SAM (SAM_B) on the via bottom, followed by another material (SAM_F) on the low-k (see figure 1). That flow enabled full elimination of ruthenium liner from the via sidewalls.
Fig. 1: After hydrogen pretreatment, a self-assembled monolayer (SAM) acts as barrier during pre-via fill using electroless deposition. Source: IITC 2022

Fig. 1: After hydrogen pretreatment, a self-assembled monolayer (SAM) acts as barrier during pre-via fill using electroless deposition. Source: IITC 2022

Interestingly, the researchers tested a pre-via-fill process, where instead of using a barrier (TaN) under the copper fill, it’s deposited after electroless deposition (ELD). More extensive testing of pre-fill vias is underway at device manufacturers to reduce resistivity, ensure reliability and extend the productivity of copper flows.

Tiny vias are the ultimate weak link in the interconnect chain. Imec and Applied Materials compared ruthenium, tungsten, and copper vias to see what resistance benefit was achieved by eliminating the bottom Ta barrier in copper relative to using tungsten or ruthenium in 24nm vias (see figure 2). [2] “The key process step is the selective ALD TaN barrier deposition on the dielectric only, after an in-situ interface engineering of the exposed copper on the bottom of the via,” said Marleen van der Veen, interconnect metallization specialist at imec. The team determined a 20% reduction in via resistance was realized by eliminating the barrier. At smaller dimensions, the reduction would be greater.

Fig. 2: Single via resistance comparing dual damascene copper reference to selective barrier copper, barrierless dual damascene ruthenium and hybrid tungsten prefill/copper shows a 20% benefit from eliminating barrier at the via bottom. Source: IITC 2022

Fig. 2: Single via resistance comparing dual damascene copper reference to selective barrier copper, barrierless dual damascene ruthenium and hybrid tungsten/copper shows a 20% benefit from eliminating barrier at the via bottom. Source: IITC 2022

Inflection point: Introducing subtractive etch
Sometime after the 2nm node, the industry is likely to change to a form of subtractive metallization from dual damascene. This represents an enormous change, and one that will not be taken lightly.

Imec’s version of subtractive metallization is called semi-damascene, because it starts with dielectric etching of trenches, similar to dual damascene. “It’s a very big step, because it’s a new module and it has risks,” said imec’s Tokei. “And then, aspect ratio can be increased gradually, and at some point air gaps can be incorporated.” The process uses a dielectric CMP step, which is similar to dielectric CMP performed at the shallow trench isolation (STI) step.

Tokei anticipates about four generations of semi-damascene processing with ruthenium, most likely. After that, binary or tertiary metal alloys may come into play. “We’ve identified several good candidates, based on resistivity and some other factors, but it’s very early R&D work,” he said. “We have about six years to really narrow it down to the best candidates.”

In semi-damascene, vias are patterned first in a dielectric stack, followed by ruthenium deposition, which overfills the feature. This metal layer is then masked and etched to form the line layer orthogonal to the via. After metal patterning, the lines can be filled with dielectric or used to form partial air gaps at the local layers. This process has a comparable cost to that of dual damascene, according to imec simulations.

So how far does copper interconnect scale? In direct comparison with ruthenium, a recent study identified the crossover point from copper to ruthenium in terms of resistivity as being just below a 300nm2, around 17 x 17nm (see figure 3).

There are different ways of fabricating air gaps, including partial gap fill or using sacrificial materials. Tokei noted, however, that achieving consistent air gap depth across the wafer on like-sized features is an industry challenge. He emphasized that air gap formation should not require an additional mask layer, but be formed as part of processing. Additionally, special attention must be paid to thermal dissipation because air is an inferior conductor.

Fig. 3: Resistivity of ruthenium drops below that of copper at <300nm2. Source: VLSI 2022

Fig. 3: Resistivity of ruthenium drops below that of copper below 300nm2. Source: VLSI 2022

There are fundamental advantages to transitioning to subtractive metallization, including no dielectric damage due to CMP and etching, the ability to go to higher aspect ratio lines (reduce resistance), and potentially simpler processes. Nonetheless, much more burden is placed on etching processes, particularly as CDs move toward 10nm metal pitch.

Lam Research and imec explored some of the challenges associated with oxygen-based ruthenium etch chemistries. [3] Typically, ruthenium is deposited by sputtering (physical vapor deposition, or PVD), then annealed around 400°C to achieve lowest resistivity. Spacer patterning in Si3N4/TiN hard masks (mandrels) is used to form tight dimensions from which to etch >3 aspect ratio ruthenium lines. A key challenge involves growth of an oxidized layer on the sidewalls of the hard mask, which significantly narrows trenches. Advanced cleaning steps and in-situ plasma cleans were implemented to remove residues and limit TiN undercut.

For molybdenum etching in a Cl2/O2 chemistry, Lam and imec determined the main problem was insufficient sidewall passivation and oxidation of the metal. The team was able to get around this by depositing thin oxide after partial molybdenum etch, and they noted that encapsulation may be necessary due to the metal’s oxidation potential.

“Based on the data, we have made more progress on ruthenium than on molybdenum,” said imec’s Tokei. “One of the concerns with molybdenum is the oxidation, which makes it better suited to a damascene type of approach. It is very interesting for middle of line, and it’s an inexpensive metal.”

Process modeling plays a key role in helping establish design rules, evaluate process windows, and ramp yield. “Virtual fabrication is a step-by-step, behavioral description of processes and process flows that is combined with critical design information to create silicon-accurate 3D models of what’s going on in the wafer,” said David Fried, vice president of computational products at Lam.

For instance, the SEMulator3D platform from Lam’s Coventor division was used to evaluate how imec’s semi-damascene flow with process boosters affects RC performance on a new mask set with metal pitches of 14nm and 16nm (1.5nm node). [4] Performance boosters, including fully self-aligned patterning, high AR metal lines, and air gaps were modeled and confirmed. Among other findings, the simulator compared different methods for via self-alignment to determine which method achieved the widest overlay tolerance at 10nm and 7nm nodes.

“Because these models have to be silicon-accurate, we spend a ton of time on calibration techniques,” Fried said. “With our baseline process model, we use machine learning techniques to do multivariate non-linear optimization of a process model, which creates a visual representation of that process. When it’s calibrated to multiple points in the process space, it becomes predictive of the rest of the process window.”

Tying in backside power
Backside power delivery (BPD) is an innovative means of delivering power to transistors from the wafer backside, freeing up the frontside interconnects to carry signals only. This relieves congestion and leading chipmakers will be implementing it at the 2nm node. “Utilizing the backside of the wafer for power distribution effectively increases the functional area of the die without increasing its footprint,” says Tom Mountsier, senior engineering director at Lam Research.

“One of the biggest challenges for backside power integration is in connecting the front and the back of the wafer electrically. That’s where TSVs come in,” Mountsier said, noting that different integration schemes are being evaluated by chipmakers. All the options involve etching and metal fill.

The most challenging scheme involves direct backside contact to the source epi. “The vias will be small and high aspect ratio,” he said. “You also need to make low resistance contact to the epi, as is done for the source/drain contacts on the frontside. Hence, tungsten fill, or possibly molybdenum, would be the likely choice. Implementation will take time due to significant integration challenges, such as aligning backside contact to the frontside epi, and making ohmic contact between the metal and epi at reduced temperature (400°C or less).”

Lam’s Assawer Soussou, senior semiconductor process engineer, summed it up: “Backside power delivery achieves a technology advantage at the cost of process complexity.”

Power delivery also has become a hot topic on the packaging side of the business. “Recently, there’s a lot of interest in photonics, especially co-packaged optics,” said Yin Chang, senior vice president of sales and marketing at ASE. “This dramatically increases the bandwidth of the data transfer. A lot of companies are reaching limitations in terms of how much bandwidth they can carry through the substrates, and if you’re not able to meet those requirements, then photonics is really the only option. So the substrate is really becoming a power delivery system.”

Dual damascene copper is being extended through 20nm pitch today, but a radical change to subtractive schemes involving ruthenium or other alternative metal is on the immediate horizon. In terms of resistivity, ruthenium becomes attractive as features dip below 17 x 17nm, which leading device makers are approaching. Companies can eke out additional gains using barrierless via bottoms while preparing for a great transition.

1. Y. Kikuchi, et. al., “Performance improvement for Cu interconnects by SAM and ELD technologies,” 2022 IEEE International Interconnect Technology Conference (IITC), 2022, pp. 126-128, doi: 10.1109/IITC52079.2022.9881316.
2. M.H. van der Veen, “Low Resistance Cu Vias for 24nm Pitch and Beyond,” pp. 129-131, doi: 10.1109/IITC52079.2022.9881285
3. S. Decoster, et. al., “ Patterning challenges for direct metal etch of ruthenium and molybdenum at 32nm metal pitch and below,” J. Vac. Science & Technology B 40, 0328802, 2022,
4. A. Soussou, “BEOL integration for the 1.5nm node and beyond,” Semiconductor Engineering, April 25, 2022,

Related Stories
Extending Copper Interconnects To 2nm
From low resistance vias to buried power rails, it takes multiple strategies to usher in 2nm chips.

Challenges In Backside Power Delivery
BPD boosts performance, but requires wafer bonding, substrate thinning, and possibly new interconnect metals.

Leave a Reply

(Note: This name will be displayed publicly)