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Challenges In Backside Power Delivery

BPD boosts performance, but requires wafer bonding, substrate thinning, and possibly new interconnect metals.

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One of the key technologies to enable scaling below 3nm involves delivering of power on the backside of a chip. This novel approach enhances signal integrity and reduces routing congestion, but it also creates some new challenges for which today there are no simple solutions.

Backside power delivery (BPD) eliminates the need to share interconnect resources between signal and power lines on the wafer frontside. Instead, as the name implies, power is moved to the back of the wafer so only signals are carried by frontside interconnects. Intel, Samsung and TSMC all have announced plans to implement BPD in some form at around the 2nm node.

In addition to relieving the RC bottleneck, BPD enables cost savings. “Backside power delivery removes the need for a power delivery track from lower layer front-side interconnects,” said Sanjay Natarajan, senior vice president and co-general manager for Logic Technology Development at Intel. “Intel then has the option to be less aggressive on interconnect scaling without skipping a beat on transistor density scaling. This allows for less complex and ultimately less expensive lower layer metal patterning.”

Fig. 1: Interconnect levels on traditional logic device (left) and backside power distribution network with PowerVia (right). Source: Intel

Fig. 1: Interconnect levels on traditional logic device (left) and backside power distribution network with PowerVia (right). Source: Intel

It also allows these different metal layers to be optimally fabricated — as wider lines for Vdd and Vss, and thinner lines to carry signals. Nonetheless, a backside power network introduces substantial wafer processing challenges — especially since the change can occur at the same node as the device maker’s switch from finFETs to nanosheet transistors.

For instance, Intel will introduce RibbonFET and PowerVia at its 20A (2nm) node “The first key challenge around PowerVia involves patterning an electrical contact feature within the tight spaces around next-generation RibbonFET transistors without impacting their performance. The second is thinning the backside silicon to deliver as direct and as low resistance a connection as possible in a repeatable and controllable manner,” said Natarajan.

Because BPD approaches are so new, the industry is weighing the pros and cons to different architectures.

Fig. 2: BPD schemes afford different scaling benefits associated with increasing levels of wafer processing complexity. Source: Applied Materials

Fig. 2: BPD schemes afford different scaling benefits associated with increasing levels of wafer processing complexity. Source: Applied Materials

BPD schemes
The ideal power delivery network delivers constant, stable supply voltage to active circuits on the IC during any activity. “The key parameter is the DC resistance of the PDN in all the interconnect paths, from the power supply pins of the IC to the transistors in the circuits.” [1]

Figure 2 shows three implementations of backside power delivery networks. “In the first approach, the logic cells retain a power rail, and the backside power distribution network is connected to the power rail by a nano TSV,” said Mehul Naik, managing director at Applied Materials. “In the second approach, there is no power rail in the logic cell. Instead, a power via directly transfers power from the backside network to the cell or the transistor contact. This approach is more complex, but it improves power efficiency and increases cell area scaling. In the third approach, power from the backside network is connected directly to each transistor’s source and drain.”

Imec was one of the first to develop a backside power delivery approach and it utilizes what it calls buried power rails (BPRs). “If we do backside power delivery network, and also for the buried power rail, there is a via from the source/drain regions, from M0 to that BPR. So we have TSVs going through the silicon and landing on the buried power rail, but the buried power rail is made even before the transistors are made. It sits in between what will be the nanosheet fins before the gate is formed and before the source/drain epi is done,” explained Eric Beyne, senior fellow, vice president of R&D, and director of the 3D System Integration Program at imec. “That is one reason why copper will never be used for this. It has to go through all the front-end processing, so it has to be compatible — something like tungsten or molybdenum, or maybe ruthenium.”

Building these into the manufacturing flow is a challenge by itself. “These power rails are made at a moment of time of the process where you have your fins or sheets defined, where the space between these fins is at its largest, because once you deposit the gate-all-around and the metal, the fin is thicker and the spacing between two neighboring fins is very narrow,” Beyne said. “So then you have to make the via very deep with an even smaller feature size.”

He noted that the short via to the backside power rail can be situated at tight spaces along the BPR, providing a good performance benefit.

The BPR runs parallel to the fin direction, and it is buried partially in the shallow trench isolation and partially in the silicon substrate. This is different from a conventional power grid with power rails in M0 or M1, and it enables standard cell height reduction.

“Intel’s PowerVia provides a more direct, single-feature connection between the backside power delivery network and a traditional source contact, that we believe can achieve much lower resistances compared to the imec approach,” said Natarajan.

Fig. 3: The power delivery network design margin permits 10% IR drop. Higher levels can threaten device performance. Source: Applied Materials

Fig. 3: The power delivery network design margin permits 10% IR drop. Higher levels can threaten device performance. Source: Applied Materials

Fig. 4: By moving the power rail, the standard cell area can be scaled by 20% to 30%. Source: Applied Materials

Fig. 4: By moving the power rail, the standard cell area can be scaled by 20% to 30%. Source: Applied Materials

Why backside power, and why now?
The reason for making this substantial change to the way power is delivered to transistors has to do with the voltage (IR) penalty, whereby electrons must travel through 15 or more layers of interconnect lines and vias on their way to delivering power and data to billions of transistors in a modern SoC. [2]  Power efficiency can reach specification limits of 90%, or 10% voltage (IR) loss between the chip’s voltage regulator and its transistors (see figure 3).

In backside power delivery, the power rails are moved outside of the logic cells, enabling logic density improvements, which Applied Materials estimates to be equivalent to as much as two generations of lithography scaling (see figure 4). Because the power is delivered directly from below the transistors, the IR drop is drastically reduced.

Simulation and fabrication studies performed by Arm and imec determined that backside power delivery can be 7X as efficient as a frontside power delivery network, provided the nanoTSVs can be positioned closer than 2µm from each other. [2]

But several process and materials changes must be realized to make BPD a reality in production fabs. “For better area usage and performance enhancement, backside power delivery (BPD) network is an attractive option. For its enablement, continuous process and tool advancement is necessary not only on film, etch, lithography and wet, but also on wafer bonding and thinning technologies,” stated Tomonari Yamamoto, vice president of device technology, Corporate Innovation Division at TEL.[3] Indeed, a number of lower resistance metals are being evaluated as potential candidates for replacing copper, which will be necessary as BEOL interconnect CDs delve below 15nm.

Fig. 5: The backside power delivery network flow requires extreme wafer thinning to <500nm atop a 50nm SiGe layer with 350nm silicon epi cap. Buried power rails of ruthenium feature 40% lower resistance than tungsten rails. Wafer-wafer bonding is followed by thinning, CMP, dry and wet etch, then TSV and M1 formation. Source: imec

Fig. 5: The backside power delivery network flow requires extreme wafer thinning to <500nm atop a 50nm SiGe layer with 350nm silicon epi cap. Buried power rails of ruthenium feature 40% lower resistance than tungsten rails. Wafer-wafer bonding is followed by thinning, CMP, dry and wet etch, then TSV and M1 formation. Source: imec

Buried power rails and BPD
The imec process flow (see figure 5) begins with epitaxial growth of SiGe and then a silicon cap layer. A high Ge concentration (25%) enables greater selectivity to CMP stop on the film. The long buried power rails are then etched in STI and extend into the silicon. Imec compared tungsten and ruthenium CVD films, the latter of which provided 40% lower resistance. The wafer is then permanently bonded to a carrier wafer using SiCN-SiCN dielectric bonding. Then the wafer undergoes backgrinding and CMP, then dry and wet etch. The SiGe is removed by chemical etch.

The wafer bonding process must be performed carefully to minimize distortion, which interferes with subsequent patterning steps. “When you do the bonding, there is a significant possibility of distortion in the pattern after bonding, and the backside patterning has to correct for these distortions,” said Beyne. “It may not be much, but even at 1ppm of scaling, which is not even 1°C in temperature, you expand the silicon and can end up with 150nm of misalignment on the wafer edges.”

Next, the nanoTSV process starts with oxide deposition (LPCVD) followed by self-aligned DUV patterning. Using advanced lithography correction methods, overlay of 100nm in x and y directions was reduced to 10nm. A Bosch etch tool creates the high AR nanoTSVs, landing on the BPR oxide and STI. Next, PECVD oxide was deposited inside the nanoTSV, followed by sputter etching of the BPR for good contact between the nanoTSVs and BPRs. TiN ALD is followed by W CVD and W CMP. Then copper damascene forms the backside metal (see figure 6).

Fig. 6: TEM cross section of passive test structure shows backside copper with 90nm nanoTSVs landing on buried power rails. Source: imec

Fig. 6: TEM cross section of passive test structure shows backside copper with 90nm nanoTSVs landing on buried power rails. Source: imec

Beyne said other difficult challenges involve backside patterning and precisely lining up the power rails and the standard cell dimensions. Whereas state-of-the-art overlay tolerance is around 3nm with EUV lithography, on the wafer backside with the distortion issues associated with wafer bonding, the overlay tolerance range is ~20nm.

“Of course, you have all the usual challenges with interconnect processing, creating high aspect ratio dimensions, depositing thin liners and barriers without voids, etc.,” he said.

Importantly, if the transistors are processed first, as occurs in all wafer fabs today, then new interconnect metals will not necessarily have to be adopted at the 2nm node. Indeed, it appears that Intel’s PowerVia allows just that. “We’ve designed our PowerVia process to be compatible with both traditional front-end contact metals (including tungsten) and advanced metal processes to get the best performance out of PowerVia,” said Natarajan.

Naik described backside power delivery network as a form of design-technology co-optimization (DTCO), where design and process innovation deliver system level benefits. He highlighted the thermal constraint that exists when the backside nanoTSVs are being built.

“We need to engineer the backside contact to the transistor source to have the lowest possible resistance,” Naik said. “This normally requires high temperature epi and anneal processes. However, because the backside contacts are being manufactured with the front-side transistors and interconnects in place, they would be degraded by these high temperatures. To manage this, Applied is developing a low-temperature solution that combines up to seven steps in high vacuum, including chambers for preclean, selective silicide deposition, ALD or PVD liner deposition, and a new metal fill. A co-optimized CMP step leaves a perfectly uniformed backside contact layer, on which we can build a copper backside power distribution network.”

Providing deposited films that adequately isolate transistors from the power network along with etch steps that approach the transistor’s active area will require precise engineering. “In etch, you want high anisotropy, defect-free and damage-free results, irrespective of which of the process flow,” said David Fried, vice president of computational products at Lam Research. “In deposition, it’s all about the material parameters that you’re trying to deposit. You want low defectivity, high throughput, and the ability to engineer those materials.”

Once companies do make the transition to backside power delivery networks, it’s important that the approach is scalable to the next process node, as well. “Our standard cell pitch is 105nm, and if you connect the nanoTSV to every other buried power rail, there’s a connection every 210nm — so 200nm lines and 200nm spacing. This is decoupled from the standard cells, so that if you scale then to 80nm, it still works and you don’t have to do EUV lithography on the backside, in this case,” Beyne said.

Next steps in minimizing RC delay
Since around the 22nm device generation, BEOL RC delay has made up a greater portion of total device delay as transistors continue scaling. For copper damascene approaches, void-free copper fill becomes more and more challenging, and ultrathin wetting and capping CVD process advancement are required.

“With copper, we can go down to something like 200nm, but you need a copper seed layer for electroplating. For nanoTSVs, tungsten and other metals scale better in high aspect ratio structures, using ALD and CVD materials, but you still need a TiN barrier metal for tungsten, for instance. At some point, you have more barrier than bulk metal, like at 30nm dimensions,” said Beyne. “Molybdenum is very attractive for some of these TSV applications because it is ALD and it deposits directly on the surface. I would say tungsten is the most common material of today. Options for improvement include ruthenium and molybdenum, but they’re still in the research phase.”

TEL’s Yamamoto had a similar view. “Ruthenium is a candidate since it is less sensitive to scattering and doesn’t need thick barrier metal, but just needs an adhesion layer with less than 1nm thickness.” He added that damascene flows tend to offer aspect ratio of 2, while subtractive etch schemes enable higher aspect ratio, which would reduce resistance, while the capacitance increase can be controlled, for instance, by replacing low-k films with air gaps.

Conclusion
Optimizing interconnect performance for a backside network is somewhat similar to that of the frontside — ensuring low resistance and long-term reliability for the backside metals. Natarajan notes, however, that by segregating power routing on the backside metal stack from signal routing on the frontside metal stack, engineers have the freedom to optimize resistance versus capacitance independently. Companies may also make different architectural choices, such as dual damascene versus subtractive processes (metal deposition and etch), depending on performance needs.

The leading device manufacturers will be incorporating backside power delivery in 2nm designs, ensuring cleaner power delivery and breaking up the RC bottleneck. A combination of advances in deposition, etch, CMP, bonding, wafer thinning, and DTCO will impact this inflection point.

References

  1. Jourdain, M. Stucchi, G. Van der Plas, G. Beyer, E. Beyne, “Buried Power Rails and Nano-Scale TSV: Technology Boosters for Backside Power Delivery Network and 3D Heterogenous Integration,” 2022 IEEE 72nd Electronic Components and Technology Conference, doi: 10.1109/ECTC51906.2022.00244.
  2. Cline, D. Presaderic, E. Beyne, O. Zografos, “Next-Gen Chips Will Be Powered from Below,” IEEE Spectrum, 26 Aug. 2021, https://spectrum.ieee.org/next-gen-chips-will-be-powered-from-below.
  3. Yamamoto, “Advanced Process Technologies for Continuous Logic Scaling Towards 2nm and Beyond,” 2022 IEEE International Interconnect Technology Conference, June 27-30, 2022, doi: 10.1109/IITC52079.2022.9881297.


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