A Power-First Approach

Power always has been a secondary optimization consideration, but in the future, it could be the most important.


It is becoming evidently clear that heat will be the limiter for the future of semiconductors. Already, large percentages of a chip are dark at any time, because if everything operated at the same time the amount of heat generated would exceed the ability of the chip and package to dissipate that energy. If we now start to contemplate stacking dies, where the ability to extract heat remains constant and the number of heat generators increases, it would appear to be a fairly bleak future.

Perhaps someone will invent a better transistor, or wires that present less resistance and capacitance. But at this point, the more obvious advances have been explored, and costs always will constrain some solutions.

For the past 40 or 50 years, optimization has been about performance and area. Power only started to become a consideration about 20 years ago, when it was realized that each percentage of performance increase came at an even greater increase in power – given the same basic architecture. It also didn’t help that Dennard scaling stopped automatically providing the same level of power savings on every new node.

Even today, when I interview people and ask if power is a primary optimization consideration, the answer is typically, “We have to meet performance metrics first and then we can worry about reducing power.” Over the next 10 years, I expect that mentality will have changed to a “power first” approach. The real question is, within a defined power budget, how much performance on a given task can I attain? You don’t get to that answer by looking at performance first.

Over the past couple decades, tools have been created that will save wasted power by performing analysis on a design and locating potential savings. Most of the time, those savings can be applied automatically and without fear of messing anything up. Examples are transistor sizing for paths that have slack, or clock gating, when it can be shown that it will have no logical impact. Other strategies are a little higher impact, such as power domain switching, where leakage currents can be eliminated in blocks when not being used. These, however, do add to the complexity of the design, and they introduce some potentially catastrophic problems that have brought some designs to their knees.

But all of these techniques are merely attempting to recover wasted power. None of them is tackling the problem head-on. What is required are power optimization strategies that influence the architecture of the system — including the algorithms that are used and potentially implemented in software running on processing platforms optimized for them, which look at the usefulness of every byte of data that is moved around a system, and so much more.

But the industry has so much momentum and inertia that change is incredibly difficult. We are seeing ever-more complex and heavyweight protocols being defined for coherence and connectivity, all of them attempts to disrupt as little as possible of the bad practices that are in place today.

There are encouraging signs. Domain-specific computing is one area that was ignited by the 2017 Turing lecture given by John Hennessy and David Patterson, and by the rapid industry adoption of the RISC-V ISA and all of the work that is surrounding that. They may not be doing it with the prime motivation being power reduction, but it is at least a start.

Another encouraging area showed up in some recent interviews I have conducted for upcoming articles on the subject of power optimization, from RTL up. When asked about the possibilities for a future in which power optimization is a primary consideration, there is passion, excitement, and hope for a better way of doing things in the future.

Twenty years ago, when the term Electronic System Level (ESL) was bandied around for the technology that would define the new age of EDA, there was lots of excitement and perhaps the heaviest investment we have seen in new EDA tools since the industry’s inception. This was an attempt to find the new abstraction, the new tools that would do for them what RTL did for Synopsys.

I got caught up in that as well, but we were all wrong. There was no new magic abstraction that would drive a new generation of designers and tools. Some good stuff did come out of it, but nothing like what was originally expected. But could we now be seeing the genesis of what will be the new era? New abstractions, flows, and tools where the primary focus is on power and energy? A new generation of design that will be able to maximize performance per watt, not through optimization, but through design?

Are there enough people who care about this planet to make that a priority? As engineers, are we in some way responsible for the energy consumption of the products we create? I do see more people who care about these things, but I also see many technological advances that are a total waste of power, where the sole motivation is profit.

Editor’s Note: If you know of any exciting developments going on in the area of tools or methodologies for power-oriented design, I would love to hear about them.


Steve Hoover says:

Hi Brian. TL-Verilog automates fine-grained clock-gating, so it’s in there from the start as a first-class citizen, not an afterthought (that gets dropped due to its eleventh-hour impact).

Peter C Salmon says:

I have proposed a thermal approach that packages a 700W Hopper H100 SXM chip using a thermal resistance from chip to coolant of 0.0074°C/W, a corresponding ΔT of 5.2°C, and an achievable power density at the system level of 2kW/cubic inch. This thermal solution can greatly reduce complexity in the design and manufacture of dense electronic systems. Please contact me if you would like to discuss. I am not a member of the Alliance.

William Ruby says:

We are beginning to see designs today that are constrained by power – i.e. that their performance is limited by maximum power consumption allowed. So ‘power first’ is here now – and what is needed is EDA technology that can guide the user in making intelligent power (and energy) driven hardware architectural decisions and software structure. Lots of opportunities for innovation!

Mike Frank says:

Dear Brian, thanks for the article. There is one scalable approach for improving power efficiency at the design level — and that’s fully adiabatic switching, which is an area I’ve been working on since the mid-90s. When it’s done right, one can boost raw throughput density within power dissipation constraints by factors of up to ~100x (and even beyond, if the process is optimized for low leakage). Please feel free to contact me for more information.

John Bennice says:

Great article Brian. Yes, energy density continues to increase as the reduction in power from the moves to more advanced nodes isn’t keeping pace with the increases in transistor density and dynamic power.
Power reduction from clock gating and DVFS isn’t dramatic enough to close the gap. I’m currently working for a company(Rezonent) that has figured out a way to recycle dissipated energy in a chip, with power savings of 30%. This can be applied across all power groups in the chip(Logic, Memory, Clock) and it has been proven in a 28nm crypto chip. Minimal area impact and no functional impact on the RTL. We would look forward to discussing with you in more detail if you are wanting to learn more.

Giovanni Lostumbo says:

Hi Brian, I sent an email on Sunday. Just mentioning it in case it may have been marked as spam. Great article.

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