Gaps Emerging In System Integration


The system integration challenge is evolving, but existing tools and methods are not keeping up with the task. New tools and flows are needed to handle global concepts, such as power and thermal, that cannot be dealt with at the block level. As we potentially move into a new era where IP gets delivered as physical pieces of silicon, this lack of an accepted flow will become a stumbling block. ... » read more

Rising To Meet The Thermal Challenge


Thermal effects on electrical performance have always existed; processor speed limits are set by thermal limits, and power has been a key concern for the mobile and datacenter markets for a decade. Increased electrical content logically generates more heat, which affects system performance. For example, in the automotive market, ADAS and infotainment systems are drastically increasing automotiv... » read more

New Approaches For Dealing With Thermal Problems


New thermal monitoring, simulation and analysis techniques are beginning to coalesce in chips developed at leading-edge nodes and in advanced packages in order to keep those devices running at optimal temperatures. This is particularly important in applications such as AI, automotive, data centers and 5G. Heat can kill a chip, but it also can cause more subtle effects such as premature aging... » read more

Benefits Of In-Chip Thermal Sensing


The latest SoCs on advanced semiconductor nodes typically include a fabric of sensors spread across the die, and for good reason. But why and what are the benefits? This first blog of a three-part series explores some of the key applications for in-chip thermal sensing and why embedding in-chip monitoring IP is an essential step to maximize performance and reliability and minimize power, or a... » read more

Power/Performance Bits: April 14


Undoped polymer ink Researchers at Linköping University, Chalmers University of Technology, University of Washington, University of Cologne, Chiba University, and Yunnan University developed an organic ink for printable electronics that doesn't need to be doped for good conductivity. "We normally dope our organic polymers to improve their conductivity and the device performance. The proces... » read more

Using Digital Image Correlation To Determine BGA Warpage


Digital image correlation (DIC) is a non-contact, full-field displacement, optical measurement technique. It is often used in the following applications: Material characterization Coefficient of thermal expansion (CTE) Glass transition temperature Young’s modulus Poisson’s ratio Sample testing for fatigue and failure In situ monitoring of displacements and str... » read more

Analog: Avoid Or Embrace?


We live in an analog world, but digital processing has proven quicker, cheaper and easier. Moving digital data around is only possible while the physics of wires can be safely abstracted away enough to provide reliable communications. As soon as a signal passes off-chip, the analog domain reasserts control for modern systems. Each of those transitions requires a data converter. The usage ... » read more

Power/Performance Bits: Jan. 7


Ferroelectric FET Researchers at Purdue University developed a ferroelectric transistor capable of both processing and storing information. The ferroelectric semiconductor field-effect transistor is made of alpha indium selenide, which overcomes the problem of ferroelectric materials not interfacing well with silicon. “We used a semiconductor that has ferroelectric properties. This way tw... » read more

Thermal Challenges In Advanced Packaging


CT Kao, product management director at Cadence, talks with Semiconductor Engineering about why packaging is so complicated, why power and heat vary with different use cases and over time, and why a realistic power map is essential particularly for AI chips, where some circuits are always on.   Interested in more Semiconductor Engineering videos? Sign-up for our YouTube channel here » read more

Finding Hotspots In AI Chips


Things are getting far more complicated as we move down to 7nm & 5nm but the tolerances of some of the physical effects that we have been measuring in the past are much tighter than they were at the older nodes. How do we track all that? What we see is that as we descend through the advanced nodes, say from 16nm down to 12nm, 7nm and more recently 5nm, we see that gate density starts to ... » read more

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