Chip Industry Week In Review


Around the world South Korea unveiled a sweeping AI and semiconductor investment drive, planning three mega projects that tie semiconductors, physical AI/robotics, and AI data centers into a single industrial plan, with government support for regional chip clusters, packaging capacity, power, water, sites, and workforce development. Among the new investments: Samsung will spend $260B on n... » read more

Blog Review: July 1


Cadence's Krunal Patel highlights auto-negotiation, a foundational feature in Ethernet that allows two connected devices to automatically determine the best possible operating parameters for a link, eliminating manual configuration and ensuring optimal performance. Synopsys' Sumit Vishwakarma warns of the rising cost of overdesign, particularly in advanced node and multi-die designs, and how... » read more

Chip Industry Week In Review


IBM unveiled a 7Å transistor architecture that uses staggered nanosheet transistors stacked on a precisely beveled angle, almost like tiles on a roof. That allows more transistors to be crammed into a given area, boosting performance by 50% or power efficiency by up to 70%. Perhaps even more important, IBM claims a 40% improvement in SRAM scaling, which is orders of magnitude faster and lower ... » read more

Executive Outlook: Agentic AI’s Impact On Chip Design


Key Takeaways: Agentic AI has the potential to make engineers more productive, speed time to market, and automate some of the drudge work. The big challenge for design and verification engineers is where and whether they trust AI to get everything right, because there is no margin for error in semiconductors. Having humans in the loop will likely be the rule rather than the exception... » read more

Blog Review: June 24


Cadence's Veena Parthan shows how finite element analysis simulations for crash testing can surpass the limitations of physical testing and offer insights into a wider array of crash scenarios that were once impossible to explore. Siemens' Haitham Eissa and Amr Khafagy warn that once-passive dummy fill structures have begun to influence design performance significantly as the industry progre... » read more

Blog Review: June 17


Cadence's Rajan Jani explains NVMe's Controller Memory Buffer feature, which exposes on-controller memory directly to the host system to reduce latency, improve PCIe fabric efficiency, and increase performance in multi-switch topologies. Siemens' Linus Tauro shares how to run an SSN datapath at double the I/O data rate by implementing a BusFrequencyMultiplier and BusFrequencyDivider pair. ... » read more

Chip Industry Week In Review


Computex in Taiwan: Arm and Nvidia introduced an AI PC platform, RTX Spark, with an Arm-based Grace CPU, Blackwell RTX GPU, and unified memory. Cadence announced a fully autonomous virtual agentic AI design engineer, enabling customers to run dynamic simulations in automated workflows. Intel launched Xeon 6+, its first data-center CPU built on Intel Foundry's 18A process. The company... » read more

Blog Review: Jun. 3


Siemens' Gordon Allan contends that verification IP gives design teams a practical way to verify standards-based interfaces and memories without rebuilding the same infrastructure generation after generation and shares key evaluation metrics. Synopsys' Sutirtha Kabir suggests that successful multi-die design will require deeper collaboration from early architecture exploration to manufacturi... » read more

Chip Industry Week In Review


ECTC Panel-level packaging, hybrid bonding, new substrates, and fine-pitch interconnects topped the list of advanced packaging technologies at ECTC this week. Among the announcements: ASE launched an automated 310mm × 310mm panel-level packaging production line. Expected to enter production in the first half of 2027, the line is compatible with FOCoS and FOCoS-Bridge pa... » read more

Blog Review: May 27


Cadence's Igor Krause explains Precision Time Measurement (PTM), a PCIe feature that enables precise coordination of events across multiple components with independent local time clocks. Siemens' John McMillan suggests the way to achieve trusted traceability across the semiconductor supply chain is by implementing a blockchain-based distributed ledger paired with a secure digital twin. Sy... » read more

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