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Revenue Soars For Semiconductor Equipment Power Subsystems


Sales of process power and reactive gas subsystems for semiconductor manufacturing equipment are on track to achieve a compound annual growth rate (CAGR) of 23% between 2016 and 2021 – far outpacing the critical subsystems industry average of 16.4% due to multiple positive factors. Process power and reactive gas subsystems account for approximately 13% of all expenditures on critical subsy... » read more

Chip Shortages Grow For Mature Nodes


The current wave of chip shortages is expected to last for the foreseeable future, particularly for a growing list of critical devices produced in mature process nodes. Chips manufactured at mature nodes typically fall under the radar, but they are used in nearly every electronic device, including appliances, cars, computers, displays, industrial equipment, smartphones, and TVs. Many of thes... » read more

Blog Review: July 21


Cadence's Paul McLellan listens in as Partha Ranganathan of Google argues that a new era of Moore's Law is emerging, defined both by the efficient design of hardware accelerators and improving the ways that hardware is utilized. Siemens EDA's Chris Spear continues exploring classes in SystemVerilog with a look at the relationship between the class variables that point to an object and how to... » read more

Week In Review: Manufacturing, Test


Chipmakers The chip industry is buzzing over a Wall Street Journal report that Intel is in talks to buy GlobalFoundries (GF) for $30 billion. In March, Intel re-entered the foundry business, positioning itself against Samsung and TSMC at the leading edge, and against a multitude of foundries working at older nodes. Intel planned to jumpstart its foundry business within its own fabs. But it... » read more

EDA, IP Numbers In Record Territory


EDA and semiconductor IP revenue soared to a new high, up 17% worldwide in Q1 compared to the same period in 2020, with revenue in China surging 73%, according to new data from SEMI's Electronic System Design Alliance. For many financial reports outside of semiconductors, strong growth numbers can be misleading because they reflect comparatively weak earnings stemming from pandemic-related s... » read more

Blog Review: July 14


Siemens EDA's Wei-Lii Tan considers the tradeoffs when running library characterization in the cloud and how to think about running CPUs in parallel, the cost of throughput, and runtime reductions. A Synopsys writer checks out the reduced blanking feature in HDMI 2.1, which can help reduce the transmission rate while keeping the resolution and refresh rate intact for higher resolution displa... » read more

CEO Outlook: Chiplets, Longer IC Lifetimes, More End Markets


Experts at the Table: Semiconductor Engineering sat down to discuss chiplets, longer IC lifetimes, and a spike in the number of end applications with Lip-Bu Tan, CEO of Cadence; Simon Segars, CEO of Arm; Joseph Sawicki, executive vice president of Siemens IC EDA; John Kibarian, CEO of PDF Solutions; Prakash Narain, president and CEO of Real Intent; Dean Drako, president and CEO of IC Manage; an... » read more

Blog Review: July 7


Cadence's Sangeeta Soni provides a primer on the PIPE SerDes architecture and some of the changes that can introduce verification challenges for SerDes compliant PHY and MAC devices. Siemens EDA's Chris Spear demystifies the $cast() method in SystemVerilog, which checks values at runtime rather than compile time, and gives some examples of when it is useful. Synopsys' Chris Clark warns th... » read more

Week In Review: Manufacturing, Test


Chipmakers and OEMs More delays and product woes at Intel. “INTC disclosed that it is delaying the launch of its next-generation Xeon server processor Sapphire Rapids (10nm) from the end of this year to 1Q22 due to additional validation needed for the chip,” said John Vinh, an analyst at KeyBanc, in a research note. “Production is expected to begin in 1Q22, with the ramp expected to begi... » read more

Blog Review: June 30


Siemens EDA's Chris Spear considers what classes should represent in SystemVerilog and offers two major categories along with some helpful UVM tips. Cadence's Paul McLellan listens in on keynotes at the recent TSMC Technology Symposium, including TSMC CEO C. C. Wei's introduction some of the fab's new offerings, such as an automotive-focused N5 process. Synopsys' Dennis Kengo Oka notes th... » read more

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