Fan-Outs vs. TSVs


Two years ago, at the annual IMAPS conference on 2.5D and 3D chip packaging, the presentations were dominated by talk of fan-out wafer-level packaging. There was almost no talk of through-silicon vias, which previously had been heralded as vital to 2.5D and 3DIC packaging. Fast forward to this month's 3D Architectures for Heterogeneous Integration and Packaging conference in Burlingame, Cali... » read more

One-On-One: Mike Muller


Arm CTO Mike Muller sat down with Semiconductor Engineering to discuss a wide range of technology and market shifts, including the impact of machine learning, where new market opportunities will show up and how the semiconductor industry will need to change to embrace them. What follows are excerpts of that conversation. SE: It's getting to the point where instead of just developing chips, w... » read more

New Drivers For I/O


Interface standards are on a tear, and new markets are pushing the standards in several directions at the same time. The result could be a lot more innovation and some updates in areas that looked to be well established. Traditionally, this has been a sleepy and predictable part of the industry with standards bodies producing updates to their interfaces at a reasonable rate. Getting data int... » read more

Mixed Messages For Mixed-Signal


There is no such thing as a purely digital design at advanced nodes today. Even designs that have no [getkc id="37" kc_name="analog"] content are likely relying on [getkc id="38" kc_name="mixed-signal"] components such as SerDes for communications, or voltage regulators for adaptive power control. But the days of purposely attempting to integrate everything including analog and RF onto a single... » read more

Move Data Or Process In Place?


Should data move to available processors or should processors be placed close to memory? That is a question the academic community has been looking at for decades. Moving data is one of the most expensive and power-consuming tasks, and is often the limiter to system performance. Within a chip, Moore's Law has enabled designers to physically move memory closer to processing, and that has rema... » read more

Exploring New Scaling Approaches


At the recent SPIE Photomask Technology + Extreme Ultraviolet Lithography 2017 conference, Semiconductor Engineering sat down to discuss semiconductor technology with Tsu-Jae King Liu, the TSMC Distinguished Professor in Microelectronics in the Department of Electrical Engineering and Computer Sciences at the University of California at Berkeley. More specifically, Liu discussed some of the new... » read more

Next-Gen Mask Writer Race Begins


Competition is heating up in the mask writer equipment business as two vendors—Intel/IMS and NuFlare—vie for position in the new and emerging multi-beam tool segment. Last year, Intel surprised the industry by acquiring IMS Nanofabrication, a multi-beam e-beam mask writer equipment vendor. Also last year, IMS, now part of Intel, began shipping the world’s first multi-beam mask writer f... » read more

New Power Concerns At 10/7nm


As chip sizes and complexity continues to grow exponentially at 7nm and below, managing power is becoming much more difficult. There are a number of factors that come into play at advanced nodes, including more and different types of processors, more chip-package decisions, and more susceptibility to noise of all sorts due to thinner insulation layers and wires. The result is that engineers ... » read more

The Week In Review: Manufacturing


Test, measurement and fab tools National Instruments (NI) has released a report that explores the future trends in the electronics industry. The report, called the NI Trend Watch 2018, looks at the technological advances and some of the biggest challenges engineers face in 2018. The report from NI looks at the following topics—machine learning; test challenges for 5G; IIoT; and effects of... » read more

Plugging Gaps In Advanced Packaging


The growing difficulty of cramming more features into an SoC is driving the entire chip industry to consider new packaging options, whether that is a more complex, integrated SoC or some type of advanced packaging that includes multiple chips. Most of the work done in this area so far has been highly customized. But as advanced packaging heads into the mainstream, gaps are beginning to appea... » read more

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