Dealing With Deadlocks


Deadlocks are becoming increasingly problematic as designs becoming more complex and heterogeneous. Rather than just integrating IP, the challenge is understanding all of the possible interactions and dependencies. That affects the choice of IP, how it is implemented in a design, and how it is verified. And it adds a whole bunch of unknowns into an already complex formula for return on inves... » read more

Avoiding Traffic Jams In SoC Design


While sitting in a traffic jam on the way to work, I realized that the sheer volume of vehicles on the road exceeds the capacity originally planned for by civil engineers, when highways first hit the drawing boards 50 or 60 years ago. It dawned on me that there is a parallel to today’s System-on-Chip design—engineers are struggling to close timing on the interconnect during the back-end pla... » read more

Safety Plus Security: A New Challenge


Nobody has ever integrated safety or security features into their design just because they felt like it. Usually, successive high-profile attacks are needed to even get an industry's attention. And after that, it's not always clear how to best implement solutions or what the tradeoffs are between cost, performance, and risk versus benefit. Putting safety and security in the same basket is a ... » read more

Automotive’s Unsung Technology


Sound systems are becoming a critical design element in vehicles, and not just for music. Thanks to evolving technology, automotive audio has reached a point where it is taking on a much broader role for applications both within and outside the vehicle. Most people associate automotive audio with the car radio, which has been a fixture in cars for decades. But in the future, these systems al... » read more

Can Formal Replace Simulation?


A year ago, [getentity id="22147" comment="Oski Technology"] achieved something that had never happened before. It brought together 15 of the top minds in [getkc id="33" kc_name="formal verification"] deployment and sat them down in a room to discuss the problems and issues they face and the ways in which they are attempting to solve those problems. Semiconductor Engineering was there to record... » read more

Automotive SoC Maker Saves Time, Enhances Product QoS For Advanced Real-Time Video Image Recognition


Automated driver assistance systems (ADAS) used to be expensive until Mobileye figured out how to use inexpensive cameras with advanced visual processing to help make cars autonomous. In this 4-page paper, created with the participation of Mobileye, you will learn how the world's #1 vision-based ADAS company uses Arteris FlexNoC interconnect IP to address demanding high bandwidth and low-latenc... » read more

The Week In Review: Design


Tools Mentor unveiled new formal-based technologies in the Questa Verification Solution. It offers formal-based RTL-to-RTL equivalence checking flows optimized for verification of manual low-power clock gating, bug fix and ECO validation, and ISO 26262 safety mechanism verification, which the company says which can reduce verification turnaround time by 10X. The app also offers expanded cloc... » read more

The Great Machine Learning Race


Processor makers, tools vendors, and packaging houses are racing to position themselves for a role in machine learning, despite the fact that no one is quite sure which architecture is best for this technology or what ultimately will be successful. Rather than dampen investments, the uncertainty is fueling a frenzy. Money is pouring in from all sides. According to a new Moor Insights report,... » read more

The Week In Review: Design


M&A Siemens closed the acquisition of Mentor Graphics, making Mentor now part of Siemens' product lifecycle management (PLM) software business. The $4.5 billion deal, announced last November, brings Siemens into the IC design tool and embedded software markets and expands Siemens' multi-physics and electronic simulation capabilities in the growing digital twin space, which ties together ... » read more

The Week In Review: Design


Tools Synopsys revealed a comprehensive low power reference kit for design and verification based on a bitcoin mining SoC design. The kit is designed to help accelerate deployment of a Unified Power Format (UPF)-based hierarchical design methodology and as a learning vehicle for the complete Synopsys low power flow. Space Codesign introduced the latest version of its simulation environmen... » read more

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