Author's Latest Posts

Use of NoC IP Facilitates Tailoring SoC Platform Design into Bespoke SoC Devices
By Arteris - 27 Jun, 2024 - Comments: 0

Customer Overview Dream Chip Technologies is a German company that originated from a research think tank initiative comprised of private companies and government-funded organizations in the beginning of 1990. The results from this effort were foundational in establishing German mastery of microelectronics. Dream Chip Technologies started as a design services provider, developing intellectua... » read more

A Configurable Test Infrastructure Using A Mixed-Language And Mixed-Level IP Integration IP-XACT Flow
By Arteris - 20 Dec, 2023 - Comments: 0

This paper written with NXP describes an efficient integration flow for mixed-language and mixed-abstraction level IPs through IP-XACT flow automation. Authors Erwin de Kock (NXP), Jos Verhaegh (NXP) and Serge Amougou (Arteris) describe: A configurable and reusable test infrastructure for RTL designs as an application of mixed-level and mixed-language integration using the IP-XACT stand... » read more

A Design Flow For Critical Embedded Systems
By Arteris - 23 Aug, 2023 - Comments: 0

Learn how IP encapsulation/packaging and interoperability using IP-XACT enabled automation in a complex verification & validation flow for aeronautical systems. Includes usage of these capabilities integrated using Arteris SoC integration technology: HW/SW codesign RTL, SystemC TLM and PSL Instruction Set Simulators Click here to read more. » read more

Innovative NoC Implementation Dramatically Speeds Derivative Design
By Arteris - 05 Jul, 2023 - Comments: 0

The Inuitive team faced a significant challenge when developing a derivative design based on the NU4000, their first vision-on-chip processor. The NU4000 employs the Advanced eXtensible Interface (AXI) on-chip communication bus protocol developed by Arm. However, removing one of the NU4000’s three vector cores resulted in access to only a limited number of AXI ports. The problem was that ... » read more

Reinventing Traceability
By Arteris - 05 Jan, 2022 - Comments: 0

This paper written by Vincent Thibault of Arteris IP describes semiconductor industry-specific problems with establishing and automating traceability between the disparate systems design teams use for requirements, specification, EDA, software engineering, verification, documentation and support. It proposes and explains the Arteris Harmony Trace solution which: Increases system quality... » read more

Using Machine Learning For Characterizations Of NoC Components
By Arteris - 06 Oct, 2021 - Comments: 0

Modern NoC (Network-on-Chip) is built of complex functional blocks, such as packet switches and protocol converters. PPA (performance/power/area) estimates for these components are highly desirable during early design phases – long before NoC gate level netlist is synthesized. At this stage a NoC component is a soft module, described by a set of architectural parameters, like the bit width of... » read more

Advanced Real‐Time Video Image Recognition
By Arteris - 02 Dec, 2020 - Comments: 0

In this 4-page paper, created with the participation of Mobileye, you will learn how the world's #1 vision-based ADAS company uses Arteris FlexNoC interconnect IP to address demanding high bandwidth and low-latency requirements. By using FlexNoC interconnect IP for its EyeQ3 and EyeQ4 product lines, Mobileye was able to address the following issues: Maintain low latency while connecting... » read more

Application Driven Network-on Chip Architecture Exploration & Refinement for a Complex SoC
By Arteris - 04 Nov, 2020 - Comments: 0

Peer-reviewed technical journal article from Springer's "Design Automation for Embedded Systems Journal."  Summarizes the various features a NoC is required to implement to be integrated in modern SoCs. Describes a top-down approach, based on the progressive refinement of the NoC description from its functional specification (Sect. 4) to its verification (Sect. 8) Click here to read more. ... » read more

CodaCache: Helping to Break the Memory Wall
By Arteris - 04 Aug, 2020 - Comments: 0

As artificial intelligence (AI) and autonomous vehicle systems have grown in complexity, system performance needs have begun to conflict with latency and power consumption requirements. This dilemma is forcing semiconductor engineers to re-architect their system-on-chip (SoC) designs to provide more scalable levels of performance, flexibility, efficiency, and integration. From the edge to data ... » read more

Power Dissipation Of The Network-On-Chip In A System-on-Chip For MPEG-4 Video Encoding
By Arteris - 04 Dec, 2019 - Comments: 0

An oldie but a goodie: Explains power benefits of NoC technology by characterizing a multi-processor system-on-chip (MPSoC) for MPEG4, AVC/H.264 encoding. Explains NoC power model used to analyze power consumption and dissipation. Includes: Description of multi-processor system-on-chip (MPSoC) for Multi-Processor System-on-Chip (MPSoC) for MPEG4, AVC/H.264 encoding Explanation of N... » read more

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