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Assuring Comprehensive Security Coverage In Hardware Design
By Arteris - 29 Apr, 2026 - Comments: 0

Is your hardware design prepared to withstand today’s complex threat landscape? Verifying the effectiveness of security functionality and protections is essential to safeguarding your designs. By adopting a systematic framework and measuring coverage throughout the pre-silicon development cycle, you can proactively identify vulnerabilities and strengthen your hardware’s resilience. Downl... » read more

Will It Blend: A Methodology for Verifying the Hardware/Software Interface in Complex SoCs
By Arteris - 28 Jan, 2026 - Comments: 0

Verification of modern System on Chip (SoC) designs involve many components. Hardware Description Languages (VHDL, System Verilog), Unified Power Format (UPF), Software Languages (C#/C++), Interconnect standards (IP-XACT, AMBA), and specialty purpose-built layers such as the Universal Verification Methodology (UVM) and System Verilog Assertions (SVA). This deck explores using Arteris SoC Integr... » read more

Making SoC Integration Simple – Achieve Higher Productivity and Quality
By Arteris - 27 Aug, 2025 - Comments: 0

The development of large-scale semiconductors has never been a simple task, but with the development of ever more powerful computers, software environments, and verification models, the task of designing cutting-edge chips becomes far more manageable. However, now that many chips being developed are utilizing as many as 1000 IP cores, the challenges of correctly connecting these modules togethe... » read more

CodaCache Last-Level Cache IP
By Arteris - 30 Jul, 2025 - Comments: 0

CodaCache Last-Level Cache (LLC) IP, is a configurable, standalone cache designed to enhance system performance, data locality, scalability, power efficiency, and cost-effectiveness in system-on-chip (SoC) designs. It aims to optimize data sharing among computing engines, accelerators, and data processing blocks by improving prefetching mechanisms to lessen reliance on main memory, thereby enha... » read more

Modernizing The Hardware / Software Interface – Life Beyond Spreadsheets
By Arteris - 28 May, 2025 - Comments: 0

The hardware/software interface (HSI) is the core of advanced semiconductor design, allowing seamless interaction between software and components like accelerators and peripherals. It underpins critical functions such as documentation, firmware, and hardware verification. Inefficient or outdated HSI management reduces collaboration, increases design errors, and threatens the performance and qua... » read more

Combination of Coherent and Non-Coherent NoCs Facilitates Cutting-Edge SoC Design
By Arteris - 23 Apr, 2025 - Comments: 0

SCALINX, a fabless semiconductor company specializing in the design of system-on-chip (SoC) devices, was looking to develop a large, next-generation SoC integrating analog, digital, mixed-signal, and RF functionality. Business Challenge • Develop a large, next-generation SoC integrating analog, digital, mixed-signal, and RF functionality. Design Challenges • Ensure different portions ... » read more

Accelerate And Derisk RISC-V- Based SoC Designs
By Arteris - 26 Mar, 2025 - Comments: 0

How to accelerate and derisk RISC-V-based SoC designs using silicon-proven network-on-chip IP and SoC integration automation software. This technology seamlessly connects any IP from multiple vendors and shortens design cycles and time to revenue. Maximize overall efficiency for the best product design, leveraging the best NoC IP and expert support. Read more here. » read more

Boost SoC Efficiency And Speed With FlexGen Smart NoC IP Automation
By Arteris - 26 Feb, 2025 - Comments: 0

Today’s high-end SoCs contain many heterogeneous processing elements to address the needs of HPC and AI applications. These include Central Processing Units (CPUs), Graphics Processing Units (GPUs), Neural Processing Units (NPUs), Tensor Processing Units (TPUs), and other hardware accelerators. Furthermore, IPs may contain clusters of these processor cores, and SoC subsystems may include arra... » read more

Accelerate AI SoC Designs with NoC Tiling
By Arteris - 30 Oct, 2024 - Comments: 0

Network-on-chip (NoC) tiling technology is revolutionizing AI and machine learning-enabled semiconductor designs. This emerging approach uses proven, robust network-on-chipIP to facilitate scaling, condense design time, speed testing and reduce design risk. It allowsSoC architects to create modular, scalable designs by replicating soft tiles across the chip. Each soft tile represents a self-con... » read more

Making Cache Coherent SoC Design Easier with Ncore
By Arteris - 28 Aug, 2024 - Comments: 0

As the number and variety of computing elements in SoCs grow, specific application areas require the tight connection of key processing elements through coherency. Ncore Interconnect IP from Arteris makes cache coherent SoC designs easier, saving 100’s of person-years effort per project vs DIY solutions. This white paper discusses the challenges and solutions in designing cache-coherent Sy... » read more

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