The Week In Review: IoT


Conferences It’s been an action-packed week at Internet of Things World. The show was co-located at the Santa Clara Convention Center with the Connected & Autonomous Vehicles conference. There were lots of deals announced and many products or services debuted at IoT World, which has grown enormously in four years, from 700 attendees at its first event in Palo Alto, Calif., in 2014 to some 14... » read more

The Week In Review: Design


M&A Consultancy Sondrel acquired IMGworks, formerly the design services unit of Imagination. Sondrel says it plans to focus on design services for ADAS systems, AI, and machine vision and learning devices. Terms of the deal were not disclosed. Tools Cadence expanded its formal verification platform, JasperGold, adding linting and clock domain crossing apps that address RTL signoff ... » read more

Notes From The Chip Beat


Over the last several months, I’ve attended a number of conferences, such as IEDM, SPIE, the FD-SOI Summit and others. At each conference, there is a dizzying amount of information and data. Eventually, some information turns into an article, while most ends up buried in a reporter’s notebook. In any case, here are five observations I’ve made, based on those and other events in the pa... » read more

Maintaining Power Profiles At 10/7nm


Understanding power consumption in detail is now a must-have of electronic design at 10nm and below, putting more pressure on SoC verification to ensure a device not only works, but meets the power budget. As part of this, the complete system must be run in a realistic manner — at the system-level — when the design and verification teams are looking at the effects of power during hardwar... » read more

Blog Review: May 17


Synopsys' Robert Vamosi digs into last Friday's massive ransomware infection that impacted the UK health system, a Spanish telecom, and many other organizations running unpatched Windows – and whether there's a second version out there. Cadence's Paul McLellan reports on the latest developments and future of FD-SOI from the SOI Silicon Valley Symposium. Mentor's Joe Hupcey III chats wit... » read more

Moore’s Law: Toward SW-Defined Hardware


Pushing to the next process node will continue to be a primary driver for some chips—CPUs, FPGAs and some ASICS—but for many applications that approach is becoming less relevant as a metric for progress. Behind this change is a transition from using customized software with generic hardware, to a mix of specialized, heterogeneous hardware that can achieve better performance with less ene... » read more

Power Challenges At 10nm And Below


Current density is becoming much more problematic at 10nm and beyond, increasing the amount of power management that needs to be incorporated into each chip and boosting both design costs and time to market. Current per unit of area has been rising since 90nm, forcing design teams to leverage a number of power-related strategies such as [getkc id="143" kc_name="dynamic voltage and frequency... » read more

Voice Recognition’s Role In Safer, More Secure Car Design


By Soshun Arai, ARM, and Mark Sykes, Recognition Technologies Look around the dashboard of a modern car and you will see dials, buttons and knobs everywhere. While each has its own purpose, they can confuse and distract people, especially when a driver should be paying attention to the road. Add to this new laws that promise harsher punishments for drivers using mobile devices, and you can s... » read more

Blog Review: May 10


Mentor's Scott Salzwedel checks out what's next for the New Horizons space probe when it comes out of hibernation later this year. Cadence's Paul McLellan provides a look at how NASA took on changing the organization's culture towards safety after the space shuttle Columbia accident. Synopsys' Robert Vamosi points to recent malware that may be affecting between 100K and 200K Windows boxes... » read more

Intel Inside The Package


Mark Bohr, senior fellow and director of process architecture and integration at Intel, sat down with Semiconductor Engineering to discuss the growing importance of multi-chip integration in a package, the growing emphasis on heterogeneity, and what to expect at 7nm and 5nm. What follows are excerpts of that interview. SE: There’s a move toward more heterogeneity in designs. Intel clearly ... » read more

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