Breaking LLMs With Fuzzing: Inside GPTFuzz’s Automated Jailbreak Machine


Software security has long relied on a technique called fuzzing, i.e. bombarding a program with malformed, unexpected, or mutated inputs until something breaks. Tools like AFL (American Fuzzy Lop) have uncovered thousands of real-world vulnerabilities this way. At Keysight, fuzzing has been a core part of security testing for years, with extensive expertise in protocol fuzzing, dedicated fu... » read more

Blog Review: July 1


Cadence's Krunal Patel highlights auto-negotiation, a foundational feature in Ethernet that allows two connected devices to automatically determine the best possible operating parameters for a link, eliminating manual configuration and ensuring optimal performance. Synopsys' Sumit Vishwakarma warns of the rising cost of overdesign, particularly in advanced node and multi-die designs, and how... » read more

Build Your Device Security Test Lab


Embedded systems are becoming more powerful, more connected, and more exposed. At the same time, attacks on hardware evolve rapidly,  expanding beyond software exploits into physical techniques such as side‑channel analysis (SCA) and fault injection (FI). Fixing hardware weaknesses late in development is costly and often impractical, and in some cases impossible once devic... » read more

Scaling Production Test Without Scaling Complexity


Production test teams often need to balance two competing priorities: improving throughput while keeping test development practical and maintainable. As product volumes increase, parallel testing becomes an attractive option because it allows multiple devices under test (DUTs) to run at the same time. In practice, however, multi-DUT execution can introduce duplicated test logic, instrument cont... » read more

UCIe vs. BoW: Practical Insights For Choosing The Right Chiplet Standards


As chiplet-based architectures gain traction across high-performance and cost-sensitive semiconductor applications, selecting the appropriate die-to-die interconnect standard has become a critical design decision. This white paper presents a practical, engineering-focused comparison of Universal Chiplet Interconnect Express (UCIe) and Bunch of Wires (BoW), highlighting their differing philosoph... » read more

Blog Review: June 24


Cadence's Veena Parthan shows how finite element analysis simulations for crash testing can surpass the limitations of physical testing and offer insights into a wider array of crash scenarios that were once impossible to explore. Siemens' Haitham Eissa and Amr Khafagy warn that once-passive dummy fill structures have begun to influence design performance significantly as the industry progre... » read more

Chip Industry Week In Review


Dealmaking Amkor inked a 10-year agreement with TSMC to provide advanced packaging and test services in Arizona, tying TSMC’s U.S. fab expansion to domestic OSAT capacity. Trump said in a post that Apple will partner with Intel on chip design and production in the U.S., marking a second reported win for the chipmaker this month. Intel Foundry will also reportedly manufacture 3 million... » read more

Blog Review: June 17


Cadence's Rajan Jani explains NVMe's Controller Memory Buffer feature, which exposes on-controller memory directly to the host system to reduce latency, improve PCIe fabric efficiency, and increase performance in multi-switch topologies. Siemens' Linus Tauro shares how to run an SSN datapath at double the I/O data rate by implementing a BusFrequencyMultiplier and BusFrequencyDivider pair. ... » read more

Chip Industry Week In Review


Notable deals Cadence and Intel Foundry inked a multi-year agreement to advance design technology co-optimization and create PDKs for Intel Foundry's 14A process. Nvidia and SK hynix announced a multi-year partnership to co-develop memory technology for AI infrastructure and physical AI. Teradyne unveiled an integrated test cell solution with TEL that supports known-good device scree... » read more

Can AI Create Missing Models?


Key takeaways Models are an essential part of EDA flows, each capturing necessary detail while retaining good execution performance. Models have been expensive to create, maintain and verify, restricting their utilization, but AI may be able to significantly reduce their cost. A deeper question remains. Should AI be used to create models that help existing flows, or should AI be used... » read more

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