Chip Industry Week In Review


The U.S. Department of Commerce and Amkor Technology signed a deal to provide up to $400 million in funding, under the CHIPS and Science Act, to build a previously announced end-to-end advanced packaging plant. The combined funding is expected to total about $2 billion. The new facility will add some 2,000 jobs in Peoria, Arizona. The SK hynix Board approved its Yongin Semiconductor Cluster... » read more

Why SoC Designers Need Purpose-Built Semiconductor IP Catalog Tools


Semiconductor intellectual property (IP) management, reuse, and change tracking are essential for efficiently creating chip designs based on proven building blocks, reducing your time-to-market, and maintaining good reputations throughout their lifetimes. Unfortunately, many SoC teams attempt to use existing tools like Git for these essential tasks, even though they are unsuitable and inconv... » read more

What’s Next In System-Level Design?


Experts At The Table: EDA has undergone numerous workflow changes over time. Different skill sets have come into play over the years, and at times this changed the definition of what it means to design at the system level. Semiconductor Engineering sat down to discuss what this means for designers today, and what the impact will be in the future, with Michal Siwinski, chief marketing officer at... » read more

Essential Insights for Design PCIe 6.0 Interconnects


PCI Express (PCIe) is a serial communication protocol that has progressed through generations to enhance data rates and functionality. The latest version, PCIe 6.0, doubles the data rate to 64 GT/s, enabling up to 256 GB/s of bandwidth in an x16 configuration. The technology incorporates PAM4 signaling and forward error correction to maintain high speeds with improved signal integrity and relia... » read more

Chip Industry Week In Review


The University of Texas at Austin’s Texas Institute for Electronics (TIE) was awarded $840 million to establish a Department of Defense microelectronics manufacturing center. This center will focus on developing advanced semiconductor microsystems to enhance U.S. defense systems. The project is part of DARPA's NGMM Program. The U.S. Dept. of Commerce announced preliminary terms with Global... » read more

Blog Review: July 17


Cadence's Xin Mu explains the PCIe ECN Unordered IO (UIO) feature in the PCIe 6.1 specification, which defines a new wire semantic and related capabilities to enable multiple-path fabric support and helps avoid unnecessary traffic for better bandwidth and latency. Synopsys' Dana Neustadter, Gary Ruggles, and Richard Solomon highlight the latest updates in the CXL 3.1 standard, including new ... » read more

Chip Industry Week In Review


The U.S. Department of Commerce issued a notice of intent  to fund new R&D activities to establish and accelerate domestic advanced packaging capacity. CHIPS for America expects to award up to $1.6 billion in funding innovation across five R&D areas, as outlined in the vision for the National Advanced Packaging Manufacturing Program (NAPMP), with about $150 million per award in each... » read more

Blog Review: July 10


Cadence's Paul Graykowski suggests using real number modeling to streamline digital mixed-signal verification using logic simulators and hardware emulators. Siemens' John McMillan and Microsoft's Amit Kumar introduce the basics of 3D-IC, describe the flow and data management challenges, look at the evolution of TSMC 3DBlox 1.0 and 2.0, and detail a physical verification and reliability analy... » read more

Securing Data In Heterogeneous Designs


Data security is becoming a bigger concern as chips are disaggregated into chiplets and various third-party IP blocks. There is no single solution that works for all designs, and no single tool or methodology that addresses everything in any design. Data is being transmitted across time zones, political borders, and even across multiple designs. Laws and the need to comply with standards may... » read more

Verification Tools Straining To Keep Up


Verification engineers are the unsung heroes of the semiconductor industry, but they are at a breaking point and desperately in need of modern tools and flows to deal with the rapidly increasing pressures. Verification is no longer just about ensuring that functionality is faithfully represented in an implementation. That alone is an insolvable task, but verification has taken on many new re... » read more

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