tag: Cadence

Week In Review: Design, Low Power
By Jesse Allen - 29 May, 2020 - Comments: 0

Tools & IP Arm unveiled several new processor IPs. Targeting next-gen smartphones, the Cortex-A78 CPU provides a 20% increase in sustained performance over Cortex-A77-based devices within a 1-watt power budget, and more efficient management of compute workloads and on-device ML. The Mali-G78 GPU provides a 25% increase in performance over the Malti-G77. It supports up to 24 cores and in... » read more

Week In Review: Auto, Security, Pervasive Computing
By Susan Rambo - 29 May, 2020 - Comments: 0

An effort to fund U.S. science and technology initiatives with at least $100 billion is getting a thumbs up from the SIA (Semiconductor Industry Association). The Endless Frontier Act —  a bipartisan, bicameral bill introduced on Thursday in the U.S. House of Representatives — will invest money into semiconductor research and development and other related fields such as material science, q... » read more

Digital Immersion: The Next Step Towards The Future Of Mobile Devices And Connectivity
By Frank Schirrmeister - 28 May, 2020 - Comments: 0

In considering how far we’ve come with mobile devices just in the last two decades, it’s entertaining to think about the next ten years. When asking the new power users, Generation Z or the “digital natives,” a couple of key themes emerge, both for mobile devices, as well as for the networks they reside in. Some key advancements have been made this week with the announcement of Arm’s ... » read more

What’s So Important About Processor Extensibility?
By Brian Bailey - 28 May, 2020 - Comments: 0

While the ability to extend a processor is nothing new, market dynamics are forcing a growing percentage of the industry to consider it a necessary part of their product innovation. From small IoT functions to massive data centers and artificial intelligence, the need to create an optimized processing platform is often the only way to get more performance or lower power out of the silicon area ... » read more

FPGA Prototyping Complexity Rising
By Ann Steffora Mutschler - 28 May, 2020 - Comments: 0

Multi-FPGA prototyping of ASIC and SoC designs allows verification teams to achieve the highest clock rates among emulation techniques, but setting up the design for prototyping is complicated and challenging. This is where machine learning and other new approaches are beginning to help. The underlying problem is that designs are becoming so large and complex that they have to be partitioned... » read more

Plan-Based Analog Verification Methodology
By Cadence - 27 May, 2020 - Comments: 0

The ability to verify all the aspects of an analog design and to keep track of all the different verification tasks is a growing challenge. Manual attempts to do so often lead to mistakes since they rely on constantly updated documents. The Cadence Virtuoso ADE Verifier provides an overarching verification plan that links to all analog tests across multiple designers. The Virtuoso ADE Verifier ... » read more

The Good And Bad Of Chiplets
By Mark LaPedus - 27 May, 2020 - Comments: 1

The chiplet model continues to gain traction in the market, but there are still some challenges to enable broader support for the technology. AMD, Intel, TSMC, Marvell and a few others have developed or demonstrated devices using chiplets, which is an alternative way to develop an advanced design. Beyond that, however, the adoption of chiplets is limited in the industry due to ecosystem issu... » read more

Blog Review: May 27
By Jesse Allen - 27 May, 2020 - Comments: 0

Mentor's Neil Johnson takes a look at achieving a practical verification methodology starting with an exclusively constrained random flow and building up by adding techniques and gauging the consequences. Cadence's Paul McLellan explains the history of neural networks and how we've been trying to mimic the brain for decades, only to see funding dry up until a sudden resurgence of annotated i... » read more

Week In Review: Design, Low Power
By Jesse Allen - 22 May, 2020 - Comments: 0

Tools & IP Cadence unveiled ten two verification IP (VIP) to support hyperscale data centers, automotive, and consumer and mobile applications. The new VIPs include complete bus functional models, integrated protocol checks and coverage models, and a specification-compliant verification plan. The VIPs cover CXL, HBM3, Ethernet 802.3ck, CSI-2 3.0, MIPI I3C 1.1, TileLink, eUSB2, UFS 3.1, MIP... » read more

Week In Review: Auto, Security, Pervasive Computing
By Susan Rambo - 22 May, 2020 - Comments: 0

Edge, cloud, data center Cadence added new verification IP (VIP) for hyperscalar data centers that supports CXL – Compute Express Link, HBM3, and Ethernet 802.3ck. The VIP are part of Cadence’s Verification Suite. Cadence also released IP for 56G long-reach SerDes on TSMC’s N7 and N6 process technologies. Many Mentor, a Siemens Business, IC design tools are now certified TSMC’s N5 a... » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2020 SMG   |  Terms of Service  |  Privacy Policy