tag: Cadence

Untangling Chip Traffic Jams
By Liz Allan - 23 Jul, 2026 - Comments: 0

Key Takeaways: Defining all possible cases of coherent and non-coherent traffic is non-trivial, and designers need to use a mix of hardware-assisted verification and simulation tools to do so. For NoCs connecting multiple dies, simulation is challenging due to the very large number of interconnects and multiphysics issues involving thermal and crosstalk. Advanced verification approac... » read more

Designing Electro-Optical Chips
By Ann Mutschler - 23 Jul, 2026 - Comments: 0

Key Takeaways: Silicon photonics is moving into mainstream AI, data center, and communications systems, but the design flow still needs tighter integration between photonic, electronic, package, thermal, and system-level tools. Existing EDA infrastructure can be reused for photonics, but waveguides, optical phase, wavelength, polarization, thermal drift, and compact modeling require spe... » read more

The Impact Of AI Automation On Chip Design
By Brian Bailey - 23 Jul, 2026 - Comments: 0

Key Takeaways: Tools are currently built with a defined notion of how they will be used. For agentic solutions they will be transformed into collections of callable engines. Agents may be built by EDA companies for design houses or larger design houses may build their own, potentially transforming the EDA business model. The role of engineers will change, but exactly how is not certa... » read more

Using Reliability Degradation Parameters To Drive Better Design Choices
By Niyati Singh - 23 Jul, 2026 - Comments: 0

A circuit can look perfect on day one and still drift out of specification after months or years of electrical and thermal stress. That is the reliability problem in a nutshell: the design does not only need to work when devices are fresh; the design must continue to meet performance expectations as devices age. A useful real-life analogy is a new car engine. A day-one test tells whether the... » read more

Blog Review: July 22
By Jesse Allen - 22 Jul, 2026 - Comments: 0

Synopsys' Dana Neustadter and Ilya Tolchinsky warn that physical AI creates a different kind of security challenge that requires continuous runtime assurance to ensure outputs remain within safe operating bounds as conditions change. Cadence's Hamid Shojaei argues that building a reliable agent for chip design relies on closing the loop, where the agent proposes something, a tool gives it ... » read more

Chip Industry Week In Review
By The SE Staff - 17 Jul, 2026 - Comments: 0

Advanced manufacturing, packaging Intel Foundry will invest €5B to expand Intel 3 capacity at its Leixlip, Ireland campus. The company also entered high-volume manufacturing for a subset of Panther Lake processors manufactured on its 18A using ASML’s High-NA EUV technology. UMC delivered the first production wafers for SILITH’s 1.6T silicon photonics platform from its 300mm Singa... » read more

Blog Review: July 15
By Jesse Allen - 15 Jul, 2026 - Comments: 0

Cadence's Anupriya K explains how Address Translation Services (ATS) acts as the fast lane for PCIe memory access by caching address translations directly on the device and what makes it one of the toughest verification problems to solve. Synopsys' Greg Sorber considers the economic potential of physical AI and the impact that embedding intelligence into robots, vehicles, and equipment will ... » read more

Chip Industry Week In Review
By The SE Staff - 10 Jul, 2026 - Comments: 0

Micron The memory maker rolled out a slew of announcements this week, including: Raised its planned U.S. investment to more than $250B through 2035, an incremental $50B above what was announced last June, with an ultimate goal of producing 40% of its DRAM in the U.S.; Planned new investments of $3B for U.S. IC supply-chain investments, including $500M in financing for GlobalWafers’ 3... » read more

AI Is Rewriting The IP Playbook
By Ann Mutschler - 09 Jul, 2026 - Comments: 0

Key Takeaways:  AI is reshaping the entire IP lifecycle, from creation and verification to discovery, licensing, and support. Fast-changing AI models are making flexible IP, robust toolchains, and faster deployment essential. Human expertise remains critical for reviewing, validating, and governing AI-assisted IP development. AI is becoming part of the everyday work of IP d... » read more

UALink Under The Hood: Why Full-Stack Verification Wins
By Sandeep Grover - 09 Jul, 2026 - Comments: 0

It is tempting to picture UALink as a clean line between two accelerators: requests enter one side, responses emerge from the other. The abstraction is useful — but it conceals almost everything that makes the protocol interesting, and almost everything that makes it difficult to verify. Verifying UALink means following a transaction the way the silicon does: down through four layers, out ... » read more

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