tag: Cadence

Designing Chips That Can Explain Themselves
By Ann Mutschler - 17 Jun, 2026 - Comments: 0

Key Takeaways: On-die telemetry gives architects a path to replace worst-case design margin with measured silicon behavior, improving PPA without compromising resilience. As monitor density and control-loop speed increase, observability must be architected hierarchically across local hardware response, on-die processing, and fleet-level learning. The real payoff is architectural: str... » read more

Blog Review: June 17
By Jesse Allen - 17 Jun, 2026 - Comments: 0

Cadence's Rajan Jani explains NVMe's Controller Memory Buffer feature, which exposes on-controller memory directly to the host system to reduce latency, improve PCIe fabric efficiency, and increase performance in multi-switch topologies. Siemens' Linus Tauro shares how to run an SSN datapath at double the I/O data rate by implementing a BusFrequencyMultiplier and BusFrequencyDivider pair. ... » read more

Chip Industry Week In Review
By The SE Staff - 12 Jun, 2026 - Comments: 0

Notable deals Cadence and Intel Foundry inked a multi-year agreement to advance design technology co-optimization and create PDKs for Intel Foundry's 14A process. Nvidia and SK hynix announced a multi-year partnership to co-develop memory technology for AI infrastructure and physical AI. Teradyne unveiled an integrated test cell solution with TEL that supports known-good device scree... » read more

DDR5 MRDIMM: A Transformational Evolution For DDR5 DIMM
By Shyam Sharma - 11 Jun, 2026 - Comments: 0

DDR5 is the latest generation of DDR server memory capable of supporting data rates of up to 9,200 Mbps, which is a huge leap over the previous generation of DDR memories. It is used in a wide variety of applications, with the huge server and data center market being the key driver behind the adoption of DDR5-based memory systems. As systems move towards more CPU cores, bandwidth, and capacity,... » read more

Building Edge AI with IP Solutions
By Cadence - 11 Jun, 2026 - Comments: 0

As AI inference moves from centralized cloud infrastructure into vehicles, factories, medical devices, and industrial systems, the decisive design challenge shifts from model quality to field-ready implementation. Deployed edge AI systems must perform reliably under a range of constraints, including fixed power budgets, stringent latency requirements, limited or intermittent cloud connectivity,... » read more

PCIe Benefits From AI, Despite Scaling Protocols
By Bryon Moyer - 10 Jun, 2026 - Comments: 0

Key takeaways: PCIe remains a critical technology for non-AI processing. For AI, PCIe will be strengthened by scale-out, agentic AI, and even some scale-up. CXL is seeing uptake, and some even think it could participate in AI processing. PCIe has been the go-to network for most data traffic moving from a processor to devices located elsewhere, which is also what the new data... » read more

Chip Industry Week In Review
By The SE Staff - 05 Jun, 2026 - Comments: 0

Computex in Taiwan: Arm and Nvidia introduced an AI PC platform, RTX Spark, with an Arm-based Grace CPU, Blackwell RTX GPU, and unified memory. Cadence announced a fully autonomous virtual agentic AI design engineer, enabling customers to run dynamic simulations in automated workflows. Intel launched Xeon 6+, its first data-center CPU built on Intel Foundry's 18A process. The company... » read more

Keeping Security Algorithms Current Is Getting Harder
By Ann Mutschler - 04 Jun, 2026 - Comments: 0

Key Takeaways: Keeping security algorithms current is now a lifecycle challenge that spans chip design, manufacturing, deployment, and long-term maintenance across the supply chain. To stay ahead of emerging threats — especially post-quantum risks — hardware must be built with cryptographic agility, secure roots of trust, and reliable update mechanisms from the start. The bigge... » read more

AI-Defined Vehicles Increase Pressure On Auto Ethernet Reliability
By Liz Allan - 04 Jun, 2026 - Comments: 0

Key Takeaways: For AI-defined vehicles and onboard agentic AI, Automotive Ethernet provides high bandwidth for sensor data fusion, TSN ensures low latency and synchronization for real-time decisions, and MACsec secures the data link. Time-sensitive networking (TSN) is an essential protocol for ensuring 10BASE-T1S delivers data to where it needs to go on time. Still, it becomes less esse... » read more

Beyond PCIe Compliance: Why Stress Testing Is Crucial For Edge AI Deployments
By Joe Chen - 04 Jun, 2026 - Comments: 0

Passing PCI Express (PCIe) compliance is different from being ready for the field. A PCIe link can clear every test in a controlled lab environment and still develop margin problems six months into deployment. That’s because a compliance traffic generator isn’t designed to replicate real-world operating conditions, such as thermal stress, electrical noise, and the kind of bursty inference t... » read more

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