Week In Review: Design, Low Power


Intel disclosed a speculative execution side-channel attack method called L1 Terminal Fault (L1TF). Leslie Culbertson, Intel's executive vice president and general manager of Product Assurance and Security, writes: "This method affects select microprocessor products supporting Intel Software Guard Extensions (Intel SGX) and was first reported to us by researchers at KU Leuven University, Techni... » read more

Big Shifts In Tech Conferences


By Ed Sperling and Katherine Derbyshire Identifying central themes in technology conferences, or finding enough latitude where the theme is extremely well defined, is becoming challenging throughout the tech industry. Throughout the semiconductor industry, in particular, many are asking how various organizations will differentiate conferences in the future and who will be the target audience... » read more

Blog Review: Aug. 15


Cadence's Paul McLellan checks out what's driving the growth of China's semiconductor industry plus the state of fab construction, from a CAPSA presentation by SEMI's Lung Chu. Mentor's Joe Hupcey III has some tips for how to handle inconclusive results in formal verification, starting with how to identify where the analysis got stuck. Synopsys' Taylor Armerding listens in on a presentati... » read more

Do Parallel Tools Make Sense?


Semiconductor Engineering sat down to talk about parallelization efforts within EDA with Andrea Casotto, chief scientist for Altair; Adam Sherer, product management group director in the System & Verification Group of Cadence; Harry Foster, chief scientist for Mentor, a Siemens Business; Vladislav Palfy, global manager for applications engineering at OneSpin; Vigyan Singhal, chief Oski for ... » read more

Power Reduction In A Constrained World


Back when 40-28nm were new, leakage power for wireless designs dominated the optimization technology focus. This led to multiple VT optimization and power intent management for digital designs to minimize or shut off leakage. As wireless devices moved to FinFET nodes, dynamic power became dominant. As a result, optimization technology focus shifted to build up dynamic techniques to complement y... » read more

Chip Aging Becomes Design Problem


Chip aging is a growing problem at advanced nodes, but so far most design teams have not had to deal with it. That will change significantly as new reliability requirements roll out across markets such as automotive, which require a complete analysis of factors that affect aging. Understanding the underlying physics is critical, because it can lead to unexpected results and vulnerabilities. ... » read more

Blog Review: Aug. 8


Cadence's Meera Collier provides a primer on the basics of quantum computing, including how quantum gates work using superpositions and how it could impact chip design. Mentor's Dennis Brophy shares a list of resources to help you get up to speed on the recently-approved Portable Test and Stimulus standard, which enables test scenarios to be run across different execution platforms. Synop... » read more

The Chiplet Race Begins


Momentum is building for the development of advanced packages and systems using so-called chiplets, but the technology faces some challenges in the market. A group led by DARPA, as well as Marvell, zGlue and others are pursuing chiplet technology, which is a different way of integrating multiple dies in a package or system. In fact, the Defense Advanced Research Projects Agency (DARPA), part... » read more

More Sigmas In Auto Chips


The journey to autonomous cars is forcing fundamental changes in the way chips are designed, tested and tracked, from the overall system functionality to the IP that goes into those systems. This includes everything from new requirements for automotive-grade chips to longer mean time between failures. But it also makes it far more challenging, time-consuming and complicated to create these d... » read more

Faster Verification With AI, ML


Tool providers have continually improved the performance, capacity, and memory footprint parameters of functional verification engines over the past decade. Today, although the core anchors are still formal verification, simulation, emulation, and FPGA-based prototyping, a new frontier focusing on the verification fabric itself aims to make better use of these engines including planning, alloca... » read more

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