Author's Latest Posts


Understanding SLAM (Simultaneous Localization And Mapping)


Amol Borkar, senior product manager for AI and computer vision at Cadence, talks with Semiconductor Engineering about mapping and tracking the movement of an object in a scene, how to identify key corners in a frame, how probabilities of accuracy fit into the picture, how noise can affect that, and how to improve the performance and reduce power in these systems. » read more

EDA In The Cloud


Michael White, director of product marketing for Calibre physical verification at Mentor, a Siemens Business, looks at the growing compute requirements at 7, 5 and 3nm, why the cloud looks increasingly attractive from a security and capacity standpoint, and how the cloud as well as new lithography will affect the cost and complexity of developing new chips. » read more

Automotive Chip Design Workflow


Stewart Williams, senior technical marketing manager at Synopsys, talks about the consolidation of chips in a vehicle and the impact of 7/5nm on automotive SoC design, how to trade off power, performance, area and reliability, and how ISO 26262 impacts those variables. » read more

Reliability In Automotive Chips


Roland Jancke, head of department for design methodology at Fraunhofer IIS’ Engineering of Adaptive Systems Division, looks at how to ensure that chips used in cars are reliable over extended periods of use, how mission profiles vary depending upon where they are used, and why it’s important to understand what chips developed at the latest nodes can really be used for and how they will be ... » read more

Week In Review: Design, Low Power


Processors Arm rolled out a micro neural processing unit that, when combined with its newest microcontroller, can increase machine learning performance by up to 480 times. The company is aiming the MCU and co-processor across a wide swath of applications. Worth noting is that Arm calls its Cortex-M55 an AI-capable processor, rather than a microcontroller, as the lines between the various proce... » read more

Where Timing And Voltage Intersect


João Geada, chief technologist at ANSYS, talks about the limitations for power delivery networks and what processors can handle, why the current solutions to these issues are causing failures, and how voltage reduction can affect timing. » read more

Thinking About AI Power In Parallel


Most AI chips being developed today run highly parallel series of multiply/accumulate (MAC) operations. More processors and accelerators equate to better performance. This is why it's not uncommon to see chipmakers stitching together multiple die that are larger than a single reticle. It's also one of the reasons so much attention is being paid to moving to the next process node. It's not ne... » read more

Changes In AI SoCs


Kurt Shuler, vice president of marketing at ArterisIP, talks about the tradeoffs in AI SoCs, which range from power and performance to flexibility, depending on whether processing elements are highly specific or more general, and the need for more modeling of both hardware and software together. » read more

Blog Review: Feb. 12


Complexity is growing by process node, by end application, and in each design. The latest crop of blogs points to just how many dependencies and uncertainties exist today, and what the entire supply chain is doing about them. Mentor's Shivani Joshi digs into various types of constraints in PCBs. Cadence's Neelabh Singh examines the complexities of verifying a lane adapter state machine in... » read more

Making Light More Reliable


The buzz around photonics in packages and between packages is growing. Now the question is whether it will work as expected, and where it will be useful. Replacing electrical with optical signals has been on the technology horizon for some time. Light moves faster through fiber than electrons through copper. How much faster depends upon the diameter of the wires, the substrate and interconne... » read more

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