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Re-using Common Simulation Set-Up Processes To Speed Regression


Functional verification of SoCs always has some kind of set up process. For complex SoCs, at least, this initial set up phase often consumes from 20 to 90% of each test’s total simulation time. And thousands of tests are run in the verification of a design. This set up phase could be either executing the exact same sequence of simulation steps, or programming the design to reach the same i... » read more

Overcoming Low Power Verification Challenges For Mixed-Signal SoC Designs


With increasing SoC complexity and advanced power-aware architectures, a robust low power verification methodology is important for signing off the design at different stages from RTL through netlist. For mixed-signal SoCs, the challenge is, there is no well-defined low power methodology, nor are the industry’s low power verification tools equipped to handle custom designs. This article propo... » read more

Reliability, Machine Learning And Advanced Packaging


Semiconductor Engineering sat down to discuss reliability, resilience, machine learning and advanced packaging with Rahul Goyal, vice president in the technology and manufacturing group at Intel; Rob Aitken, R&D fellow at Arm; John Lee, vice president and general manager of the semiconductor business unit at ANSYS; and Lluis Paris, director of IP portfolio marketing at TSMC. What follows ar... » read more

So Many Waivers Hiding Issues


Semiconductor Engineering sat down to discuss problems associated with domain crossings with Alex Gnusin, design verification technologist for Aldec; Pete Hardee, director, product management for Cadence; Joe Hupcey, product manager and verification product technologist for Mentor, a Siemens Business; Sven Beyer, product manager design verification for OneSpin; and Godwin Maben, applications en... » read more

Planning Out Verification


OneSpin Solutions’ Nicolae Tusinschi talks with Semiconductor Engineering about how to move from specification to signoff in a verification flow. https://youtu.be/2zrgaq2I1SQ » read more

Next-Generation Liberty Verification And Debugging


Accurate library characterization is a crucial step for modern chip design and verification. For full-chip designs with billions of transistors, timing sign-off through simulation is unfeasible due to run-time and memory constraints. Instead, a scalable methodology using static timing analysis (STA) is required. This methodology uses the Liberty file to encapsulate library characteristics such ... » read more

Accelerate SoC Simulation Time of Newer Generation FPGAs


Comprehensive verification that can be provided by HDL simulators is good, but not ideal. What is necessary is a faster, safer, and more thorough verification environment that combines the robustness of an HDL simulator with the speed of FPGA prototyping boards. The goal is to put together the power of these two verification methodologies into one platform. Read more. » read more

Auto Chip Design, Test Changes Ahead


The automotive industry’s unceasing demand for performance, coupled with larger and more complex processors, are driving broad changes in how electronics are designed, verified and tested. What's changing is that these systems, which include AI-oriented logic developed at the most advanced process nodes, need to last several times longer than traditional IT and consumer devices, and they n... » read more

Solving Puzzling Power-Aware Coverage: Getting An Aggregated Coverage Metric


Coverage metrics tell us when a design has been thoroughly verified, or at least exercised to the point of diminishing returns. Rarely can every design artifact or design parameter of a highly complex design be covered 100 percent, but we can use coverage metrics to know the extent to which we have verified the design — enough to be confident that it will function as desired in the end produc... » read more

Low Power Coverage: The Missing Piece In Dynamic Simulation


Through real design examples and case studies, this paper demonstrates how to achieve comprehensive low power design verification closure with all possible sources of power states, their transition coverage, and cross-coverage of power domains of interdependent states. As well the paper proposes a mechanism to combine and represent LP and non-LP coverage in a unified and adaptable database with... » read more

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