tag: verification

A Self-Evolving Agent Framework That Treats Hardware Design as Repository-Level Code Evolution (Nvidia Research)
By Technical Paper Link - 30 Jun, 2026 - Comments: 0

A new technical paper, Agentic Hardware Design as Repository-Level Code Evolution, was published by researchers at Nvidia Research. Abstract "We present HORIZON, a self-evolving agent framework that treats hardware design as repository-level code evolution. A Markdown harness is compiled into a project pack containing domain knowledge, an executable evaluator, an acceptance predicate, and... » read more

Rethinking Chip Verification
By Ann Mutschler - 29 Jun, 2026 - Comments: 0

Key Takeaways: AI and modern tools are easing traditional verification pain, but they're not addressing the underlying bottleneck in complex designs. Work is underway to create a golden, unambiguous spec above RTL, tracing requirements from spec to implementation to verification and checking for gaps, conflicts, and inconsistencies across levels and blocks, often with AI help. Tool c... » read more

Verification Methodologies Struggle To Keep Up With AI
By Brian Bailey - 25 Jun, 2026 - Comments: 0

Key Takeaways:  The rapid development of AI has resulted in new capabilities being provided to verification teams, beyond their ability to rationally insert them into accepted methodologies.  There is a lot of uncertainty about who will benefit the most from this technology. Is AI a junior engineer replacement or an enhancer?  The biggest benefits will come when AI helps engineers... » read more

How Far Left Can We Really Shift Verification?
By Frank Schirrmeister - 25 Jun, 2026 - Comments: 0

"Shift left" has been in the engineering lexicon for so long that it risks becoming wallpaper. We nod at it, we put it on slides, and we move on. But the goalposts keep moving. Things that used to live comfortably at the tail end of the design flow — software bring-up, power and performance characterization, thermal analysis — are being dragged earlier and earlier into the schedule, driven ... » read more

How Far Left Can You Shift?
By Ed Sperling - 24 Jun, 2026 - Comments: 0

More steps in the design flow are shifting left, which makes a complicated design process even more complex. This includes early software prototyping, workload mapping, verification, multi-physics integration, verification, IP qualification. Frank Schirrmeister, executive director of strategic programs for System Solutions at Synopsys, talks about the increasing number of steps, the potential t... » read more

Can AI Create Missing Models?
By Brian Bailey - 11 Jun, 2026 - Comments: 0

Key takeaways Models are an essential part of EDA flows, each capturing necessary detail while retaining good execution performance. Models have been expensive to create, maintain and verify, restricting their utilization, but AI may be able to significantly reduce their cost. A deeper question remains. Should AI be used to create models that help existing flows, or should AI be used... » read more

Mastering 3D-IC Verification Complexity
By Matt Grange - 11 Jun, 2026 - Comments: 0

The semiconductor industry's transition from traditional 2D integrated circuits to 2.5D and 3D-IC configurations represents more than an incremental advancement. This architectural shift, driven by the need to push beyond conventional scaling limitations, introduces a cascade of verification challenges that legacy methodologies struggle to address. As designs incorporate multiple stacked dies, ... » read more

Disturbance In Verification
By Brian Bailey - 08 Jun, 2026 - Comments: 3

When writing my recent story about agentic verification, there was one quote from Abhi Kolpekwar, senior vice-president and general manager at Siemens EDA, that really struck a chord. He was talking about the additional token costs that would be consumed when a verification engineer starts asking the agents to do what was considered to be part of their job. "Consider the total cost of owners... » read more

From Circuits to Systems: Unlocking the Power of Periodic Steady-State Analysis (eBook)
By Cadence - 03 Jun, 2026 - Comments: 0

RF and mixed-signal design verification is getting harder. Heterogeneous integration means sensitive RF blocks now sit next to noisy digital logic. Advanced-node CMOS means analog functions are increasingly implemented with fast-switching digital circuits. Wireless standards keep evolving, and the documentation runs hundreds of pages. Our new ebook, From Circuits to Systems: Unlocking the P... » read more

Toward Agentic Verification
By Brian Bailey - 28 May, 2026 - Comments: 1

Key Takeaways: Agentic verification provides flow orchestration for common repetitive tasks. Capabilities will expand when tools can learn from a larger context, including the specification. Design houses need to fully understand the costs and benefits and plan accordingly. Agentic verification is more than a buzzword. It is a pivotal moment in the evolution of verification ... » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy