Variables Complicate Safety-Critical Device Verification


The inclusion of AI chips in automotive and increasingly in avionics has put a spotlight on advanced-node designs that can meet all of the ASIL-D requirements for temperature and stress. How should designers approach this task, particularly when these devices need to last longer than the applications? Semiconductor Engineering sat down to discuss these issues with Kurt Shuler, vice president of... » read more

Gaps Emerging In System Integration


The system integration challenge is evolving, but existing tools and methods are not keeping up with the task. New tools and flows are needed to handle global concepts, such as power and thermal, that cannot be dealt with at the block level. As we potentially move into a new era where IP gets delivered as physical pieces of silicon, this lack of an accepted flow will become a stumbling block. ... » read more

And The Survey Says…


Some of you may have received an email recently that looks something like this. Others may be getting it in a little while. This is an invitation to participate in a survey that is important for the industry, and I encourage you not to ignore it. Let me explain a little. This survey has quite a long history. It all started in 2002 when Collett International conducted the first survey. Ba... » read more

Over-Design, Under-Design Impacts Verification


Designing a complex chip today and getting it out the door on schedule and within budget — while including all of the necessary and anticipated features and standards — is forcing engineering teams to make more tradeoffs than in the past, and those tradeoffs now are occurring throughout the flow. In an ideal system design flow, design teams will have done early, pre-design analysis to se... » read more

2020 CEO Outlook


Semiconductor Engineering sat down to discuss the semiconductor industry's outlook and what's changing with Simon Segars, CEO of Arm; Joseph Sawicki, executive vice president of IC EDA at Mentor, a Siemens Business; Raik Brinkmann, CEO of OneSpin Solutions; Babak Taheri, CEO of Silvaco; John Kiberian, CEO of PDF Solutions; and Prakash Narain, CEO of Real Intent. The conversation was part of the... » read more

EDA In The Cloud — Why Now?


What is the value of cloud computing to my company? Learn how the cloud became a viable option for IC verification, and explore the ways your company can best use cloud resources to expand your compute options for both established nodes and leading-edge technologies. To read more, click here. » read more

Simplifying And Speeding Up Verification


Semiconductor Engineering sat down to discuss what's ahead for verification with Daniel Schostak, Arm fellow and verification architect; Ty Garibay, vice president of hardware engineering at Mythic; Balachandran Rajendran, CTO at Dell EMC; Saad Godil, director of applied deep learning research at Nvidia; Nasr Ullah, senior director of performance architecture at SiFive. What follows are excerpt... » read more

Using Calibre For Advanced IC Packaging Verification And Signoff


As high density advanced package designs evolve and become more common, an automated LVS-like flow to detect and highlight package connectivity errors is required. We explain the most common package verification issues and how designers can resolve them using using Xpedition Substrate Integrator and Calibre 3DSTACK to provide a significant advantage over traditional LVS flows for HDAP. To re... » read more

Faster Formal Verification Closure For Datapaths In AI Designs


In recent years, many longstanding assumptions about formal verification have been rendered obsolete by ever-improving technology. Applications such as connectivity checking have shown that formal can work on large system-on-chip (SoC) designs, not just small blocks. Standard SystemVerilog Assertions (SVA) have eliminated the need to learn an abstruse mathematical language for each new formal t... » read more

Rethinking Your Approach To Radiation Mitigation


Formal verification and automation provide an effective, high quality, and repeatable process for fault analysis, protection, and verification for FPGA designs used in high radiation environments. This paper describes an automated systematic approach based on formal verification structural and static analysis that identifies design susceptibility to radiation induced faults. To read more, clic... » read more

← Older posts