tag: verification

The 3D-IC Multiphysics Challenge Dictates A Shift-Left Strategy
By John Ferguson - 25 Apr, 2024 - Comments: 0

As the industry marches forward in a 3D-IC centric design approach (figure 1), we are facing a new problem. Sometimes referred to as “electro-thermal” or “electro-thermo-mechanical,” it really is the confluence of multiple forms of physics exerting impacts on both the physical manufacture and structure of these multi-die designs and their electrical behavior. Fig. 1: Illustration... » read more

Verification In Crisis
By Ashish Darbari - 25 Apr, 2024 - Comments: 0

Why is it still so hard to ensure good quality sign-off happens without leaving behind bugs in silicon? The answer, according to my colleagues at DVCon, is highly nuanced. The industry has been improving overall, as has the complexity of designs. For ASICs, 74% of the designs surveyed in the recent Wilson Research Group/Siemens EDA report have one or more processor cores, 52% have two or mor... » read more

Reduce 3D-IC Design Complexity: Early Package Assembly Verification
By Siemens EDA - 24 Apr, 2024 - Comments: 0

Uncover the unique challenges, along with the latest Calibre verification solutions, for 3D-IC design in this new technical paper. As 2.5D and 3D-ICs redefine the possibilities of semiconductor design, discover how Siemens is leading the way in verifying complex multi-dimensional systems, while shifting verification left to do so earlier in the design process. What you'll learn: Overcom... » read more

Scalable Verification of Memory Consistency (Purdue University)
By Technical Paper Link - 06 Apr, 2024 - Comments: 0

A new technical paper titled "QED: Scalable Verification of Hardware Memory Consistency" was published by researchers at Purdue University. Abstract "Memory consistency model (MCM) issues in out-of-order-issue microprocessor-based shared-memory systems are notoriously non-intuitive and a source of hardware design bugs. Prior hardware verification work is limited to in-order-issue processors... » read more

Engineers Or Their Tools: Which Is Responsible For Finding Bugs?
By Ann Mutschler and Adam Kovac - 28 Mar, 2024 - Comments: 0

Experts at the table: Finding and eliminating bugs at the source can be painstaking work, but it can prevent bigger problems later in the design flow, when they are more difficult and expensive to fix.  Semiconductor Engineering sat down to discuss these issues with Ashish Darbari, CEO at Axiomise; Ziyad Hanna, corporate vice president R&D at Cadence; Jim Henson, ASIC verification software... » read more

Navigating Design Challenges
By Siemens EDA - 28 Mar, 2024 - Comments: 0

Explore the future of IC design with the Calibre Shift left initiative. In this paper, author David Abercrombie reveals how Siemens is changing the game for block/chip design-stage verification by moving Calibre verification and reliability analysis solutions further left in the design flow, including directly inside your P&R tool cockpit. Discover how you can reduce traditional long-loop v... » read more

LLMs For EDA, HW Design and Security
By Technical Paper Link - 12 Mar, 2024 - Comments: 0

A new technical paper titled "Hardware Phi-1.5B: A Large Language Model Encodes Hardware Domain Specific Knowledge" was published by researchers at Kansas State University, University of Science and Technology of China, Michigan Technological University, Washington University in St. Louis and Silicon Assurance. Abstract "In the rapidly evolving semiconductor industry, where research, design... » read more

Overcoming The Challenges Of Verifying Multi-Die Systems
By Synopsys - 12 Mar, 2024 - Comments: 0

Despite clear advantages of multi-die systems, the decision to design a multi-die system rather than a traditional monolithic SoC is not easy. There are numerous new challenges that stand in the way of multi-die system realization. This white paper focuses on the verification challenges of multi-die systems, including: Addressing capacity and performance for system verification Valid... » read more

Accellera Preps New Standard For Clock-Domain Crossing
By Brian Bailey - 29 Feb, 2024 - Comments: 0

Part of the hierarchical development flow is about to get a lot simpler, thanks to a new standard being created by Accellera. What is less clear is how long will it take before users see any benefit. At the register transfer level (RTL), when a data signal passes between two flip flops, it initially is assumed that clocks are perfect. After clock-tree synthesis and place-and-route are perfor... » read more

Weak Verification Plans Lead To Project Disarray
By Anika Sunda - 29 Feb, 2024 - Comments: 0

The purpose of the verification plan, or vplan as we call it, is to capture all the verification goals needed to prove that the device works as specified. It’s a big responsibility! Getting it right means having a good blueprint for verification closure. However, getting it wrong could result in bug escapes, wasting of resources, and possibly lead to a device failing altogether. With the foc... » read more

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