Virtual Verification Of Computational Storage Devices


Over recent years, there has been a move to replace hard-disk drive (HDD) storage with solid-state drive (SSD) storage. SDDs are faster, contain no moving parts that can fail or be affected by environmental hazards, and the cost of SSDs has been dropping each year. Unfortunately, the verification of an SSD is quite complex. In particular because of hyperscale datacenter enterprise and client-dr... » read more

Week In Review: Design, Low Power


Tools & IP Cadence debuted System-Level Verification IP (System VIP), a suite of tools and libraries for automating SoC testbench assembly, bus and CPU traffic generation, cache-coherency validation, and system performance bottleneck analysis. Tests created using the System VIP solution are portable across Cadence simulation, emulation and prototyping engines and can also be extended to po... » read more

Machine Learning Enabled High-Sigma Verification Of Memory Designs


Emerging applications and the big data explosion have made memory IPs ubiquitous in modern-day electronics. Specifically, the demand for memories with low-die area, low voltage, high capacity, and high performance is rising for use by data center and cloud computing servers. This is essential to serve the exponentially growing connectivity boom and the latest emerging 5G based systems, includin... » read more

Effective Clock Domain Crossing Verification


As chips grow ever larger and more complex, gate count and amount of embedded memory grow dramatically. The number of clock domains is also increasing steadily. Several dozen different clocks are common in today’s chips, with some designs having more than a thousand domains. There are several reasons for this explosion: Multiple external interfaces with distinct clock requirements Lic... » read more

Searching For Power Bugs


How much power is your design meant to consume while performing a particular function? For many designs, getting this right may separate success from failure, but knowing that right number is not as easy as it sounds. Significant gaps remain between what power analysis may predict and what silicon consumes. As fast as known gaps are closed, new challenges and demands are being placed on the ... » read more

I’m Almost Done


The city of Belgrade is renovating the street where I live. They are also building a new building next to mine so that I can see the construction work from my balcony. Last week, they blocked the street for some 20 minutes, and people got out of their cars and waited outside for the road to open. The construction workers were not in a hurry, and it seemed like everyone was ok with that, so I... » read more

RISC-V: Will There Be Other Open-Source Cores?


Part 3: Semiconductor Engineering sat down to discuss the business and technology landscape for RISC-V with Zdenek Prikryl, CTO of Codasip; Helena Handschuh, a Rambus Security Technologies fellow; Louie De Luna, director of marketing at Aldec; Shubhodeep Roy Choudhury, CEO of Valtrix Systems; and Bipul Talukdar, North America director of applications engineering at SmartDV. What follows are exc... » read more

Tackling Functional Correctness, Safety, Trust And Security


We’re six months into the pandemic, and it looks like in-person conferences are becoming a distant memory and that virtual conferences are now becoming routine. It used to be that traveling to a conference (sometimes long distances) was the only way to be able to attend technical presentations and learn about the latest technologies and methodologies, and that was only if you received permiss... » read more

Innovative Strategies Are Improving Early Design Circuit Verification


Layout vs. schematic (LVS) circuit verification is an essential stage in the integrated circuit (IC) design verification cycle. However, given today’s large design sizes, numerous hierarchies, and complex foundry decks, meeting planned tapeout deadlines in the quickest turnaround time (TAT) can be difficult. In an effort to minimize TAT, most design teams now use parallelized design flows, wh... » read more

New Uses For Assertions


Assertions have been a staple in formal verification for years. Now they are being examined to see what else they can be used for, and the list is growing. Traditionally, design and verification engineers have used assertions in specific ways. First, there are assertions for formal verification, which are used by designers to show when something is wrong. Those assertions help to pinpoint wh... » read more

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