Big Growth Areas: Connectivity, AI, Reliability


Connectivity and artificial intelligence (AI) will be the biggest drivers for 2020, with an emphasis on improved reliability across all areas. New standards, new applications, and new pressures being placed on old technology will created boundless opportunities for those ready to fill the need. Of course, there will also be a lot of carnage along the way, and we can expect to see a lot of that ... » read more

Using Automotive IP For Easier Integration Of Safety Into SoCs


By Shivakumar Chonnad and Vladimir Litovtchenko Today’s SoCs for automotive safety-related systems integrate numerous IP blocks. At the system level, the Hardware Software Interface (HSI) between these IP blocks needs to be verified in simulation and validated in prototype. However, the scaling of the scope and effort to verify or validate is not linear based on the growing complexity of S... » read more

Building A State-of-the-Art Verification Environment


The key challenge: Build an environment with state-of-the-art verification technologies, as a model case for succeeding projects, with: • Maximum reuse of legacy IP cores and verification environments • Short turnaround time • High-quality results The customer: A global leader in microcontroller (MCU), analog, power, and system-on-chip (SoC) products, Renesas Electronics Corporation... » read more

Applications, Ecosystems And System Complexity Will Be Key Verification Drivers For 2020


In my predictions blog last year, I focused on verification throughput and its expected growth in 2019. The four areas I predicted we’d see growth in during 2019 were scalable performance, unbound capacity including cloud enablement, smart bug hunting and multi-level abstractions. In 2018, the five key verification drivers that I identified were security, safety, application specificity, proc... » read more

Will Open-Source Processors Cause A Verification Shift?


While the promised flexibility of open source could have advantages and possibilities for processors and SoCs, where does the industry stand on verification approaches and methodologies from here? Single-source ISAs of the past relied on general industry verification technologies and methodologies, but open-source ISA-based processor users and adopters will need to review the verification flows... » read more

When Is Robustness Verification Complete?


Understandably, hardware designed for an aircraft, or indeed any safety critical application, must be robust. I also believe that all engineers wish to verify their designs as thoroughly as possible, anyway. However, there are limiting factors; most notably the high complexity of most designs. Since we are unable to discover and verify the design against all abnormal conditions, the main questi... » read more

Verifying Security In Processor-based SoCs


By Ruud Derwig and Nicole Fern Security in modern systems is of utmost importance. Device manufacturers are including multiple security features and attack protections into both the hardware and software design. For example, the Synopsys DesignWare ARC Processor IP includes many security functions in its SecureShield feature set. End-product system security, however, cannot be guaranteed by ... » read more

Interdependencies Complicate IC Power Grid Design


Creating the right power grid is a growing problem in leading-edge chips. IP and SoC providers are spending a considerable amount of time defining the architecture of logic libraries in order to enable different power grids to satisfy the needs of different market segments. The end of Dennard scaling is one of the reasons for the increased focus. With the move to smaller nodes, the amount of... » read more

A UFS Verification Closure Flow Using The Synopsys Verification Continuum Platform


It's a longstanding cliche, but it is true that “there is no silver bullet for functional verification.” No single tool or methodology can find and shoot down all the bugs in a large, complex semiconductor design. Simulation is well understood but can be slow for today's large SoCs. Emulation hardware is fast, but expensive enough that it is usually shared across a verification team. Formal... » read more

Distributed Design Implementation


PV Srinivas, group director for R&D at Synopsys, talks about the impact of larger chips and increasing complexity on design productivity, why divide-and-conquer doesn’t work so well anymore, and how to reduce the number of blocks that need to be considered to achieve faster timing closure and quicker time to market. » read more

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