Clock Domain Crossing Signoff Through Static-Formal-Simulation


By Sudeep Mondal and Sean O'Donohue Clocking issues are one of the most common reasons for costly design re-spins. This has been the driving factor in the ever-increasing demand for Clock Domain Crossing (CDC) analysis tools. Today, the majority of IP and SoC teams are focusing on “Structural CDC” analysis, which is important but not sufficient. Structural CDC analysis ensures that the d... » read more

Synthesizing Hardware From Software


The ability to automatically generate optimized hardware from software was one of the primary tenets of system-level design automation that was never fully achieved. The question now is whether that will ever happen, and whether it is just a matter of having the right technology or motivation to make it possible. While high-level synthesis (HLS) did come out of this work and has proven to be... » read more

Improving Verification Predictability And Efficiency Using Big Data


By providing a Big Data infrastructure, with state of the art technologies, within the verification environment, the combination of all verification metrics allows all resources to be used as efficiently as possible and enables process improvements using predictive analysis. This paper covers the technology, the metrics, and the process, and it will explore a number of techniques enabled by suc... » read more

Debug Tools Are Improving


Semiconductor Engineering sat down to discuss debugging complex SoCs with Randy Fish, vice president of strategic accounts and partnerships for UltraSoC; Larry Melling, product management director for Cadence; Mark Olen, senior product marketing manager for Mentor, a Siemens Business; and Dominik Strasser, vice president of engineering for OneSpin Solutions. Part one can be found here. Part two... » read more

Reusable UPF: Transitioning From RTL To Gate Level Verification


This paper highlights the differences between an RTL UPF and a Gate Level Simulation UPF, and presents a new methodology to write RTL UPF in such a way that minimal changes are required during gate-level power verification. To read more, click here. » read more

A Holistic View Of RISC-V Verification


Last month, we discussed the growth of the RISC-V open processor ecosystem, the two main organizations driving it, and the role that OneSpin plays. In addition, we have become very active in the RISC-V community and have more than a dozen technical articles published, conference talks presented, and upcoming talks accepted. We tend to focus on the challenges of verifying RISC-V IP cores and sys... » read more

Inferencing At The Edge


David Fritz, head of corporate strategic alliances at Mentor, a Siemens Business, shows how to apply YOLO (you only look once) at the edge, allowing automotive companies to move from a GPU to a much more efficient processor. That allows inferencing to move much closer to the sensor, so neural networks can be tailored to the type of data being produced. From there the data can be abstracted and ... » read more

Signoff-Compatible CDC


Tanveer Singh, senior staff consulting applications engineer at Synopsys, explains why netlist clock domain crossing is now an essential complement to RTL CDC, why CDC issues are worse at advanced nodes and in AI chips, and why dealing with CDC effectively is becoming a competitive requirement for performance and low power. » read more

Verification Requirements For 5G To Enable A Perfect Storm Of New Applications


In my role as product management lead, to understand drivers for verification requirements and semiconductor markets I often exchange thoughts with customers what they think the next “killer app” would be. Ten years back, the drivers seemed pretty clear and segmented on a small number of applications, but the outlook today in 2019 is much more diverse. 5G networking seems to be a binding el... » read more

Hybrid Emulation Takes Center Stage


From mobile to networking to AI applications, system complexity shows no sign of slowing. These designs, which may contain multiple billion gates, must be validated, verified and tested, and it’s no longer possible to just throw the whole thing in a hardware emulator. For some time, emulation, FPGA-based prototyping, and virtual environments such as simulators have given design and verific... » read more

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