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Optimizing Tool Integration Is Essential To Design Success


By James Paris and Armen Asatryan The relationship between a place and route (P&R) application and the collection of system-on-chip (SoC) design implementation, analysis, and verification methodologies and tools has always been very much a two-way street. The P&R system is the base, if you will, of design implementation—it takes the virtual and makes it physical. However, it is use... » read more

Interface DRC Can Streamline Chip-Level Interface Physical Verification


In most design companies, the chip-level physical implementation teams responsible for design floorplanning in place and route (P&R) environments also manage top-level physical verification from the early floorplanning stages through tapeout. In early floorplanning stages, blocks placed in the chip-level floorplan are usually still under development. Merging these incomplete blocks with the... » read more