Robust Dynamic Voltage Droop Mitigation And Power Management

Power management is one of the keys for developing successful semiconductors products. There are virtually no applications for which power consumption is not a concern. Many creative solutions have been developed to reduce and manage power. Making these schemes work robustly in real-world conditions can be a challenge. This post considers widely used methods—voltage droop/glitch detection and dynamic voltage and frequency scaling (DVFS/DFS)—and how they both mitigate droop effects and enable power management within a system on chip (SoC).

Power challenges

The need to keep power consumption as low as possible is clear for any portable, battery-powered device. Cell phones are literally lifelines in remote locations, and if they are drained the consequences can be serious. For power-hungry applications such as high-performance computing (HPC) and AI, consumption matters even more. Data centers are located next to hydroelectric dams and restarted nuclear power plants just to meet demand. Cooling costs are enormous. Anything that can save power with minimal effect on performance is highly desirable.

The power to all parts of the SoC is provided by the power delivery network (PDN). There is a real-world wrinkle that makes it challenging to maintain the desired power level. The high switching activity in high performance applications can cause voltage droop, which occurs when the current draw temporarily exceeds the capabilities of the PDN. Rapid short-term drops in supply voltage lead to timing violations and, in extreme cases, a reset of the processing core(s). Ameliorating the effects of voltage droop is also highly desirable.

Power reduction techniques start at the silicon level with circuit design and range all the way up to software-level juggling of tasks. DVFS is a comprehensive approach that spans multiple levels. It is a combination of dynamic voltage scaling (DVS) and dynamic frequency scaling (DFS). With DVS, the operating voltage is scaled up or down in response to the current workload. Similarly, DFS adjusts the operating clock speed to match the workload. DVFS can be applied for individual blocks, major subsystems such as processors, and even entire SoCs.

One way to compensate for voltage droop is to scale the frequency down to reduce power demand, keeping current draw within the limits of the PDN. Because DVFS has the capability of scaling frequency as well as voltage, it is possible to include droop mitigation as part of its functionality. A droop detector can trigger the immediate action of scaling the clock frequency down. The frequency then automatically ramps back to normal as the voltage level recovers, smoothly to avoid self-induced droops due to rapid changes in frequency.

An available solution

SLM Advanced Clock Generator (ACG) IP from Synopsys is a clock generation system that provides a ground-up approach to localized clock management and DVFS while including the capability to mitigate functional failures caused by workload-induced voltage. The IP serves as a high performance fractional PLL, featuring three independent oscillators, enabling the provision of multiple frequency domains. Beyond support for DVFS and fine-grained clocking, ACG can mitigate voltage droop by scaling voltage when paired with an appropriate droop detector.

The block diagram of the ACG is shown below. It accepts inputs from a droop/glitch detector (GD) and a temperature sensor to respond to real-time silicon status. It is configured and controlled over an APB bus and an IEEE 1687 instrumentation interface. Software task managers can program the ACG to scale frequencies up or down based on the current workload. Power management hardware beyond the droop detector and temperature sensor can also make changes to clocking using these interfaces.

The ACG is the most flexible and responsive SoC clocking solution on the market. It provides ultra-fast adaptive clocking; extensive programmability to address varied use cases, architectures, and workloads; and observability to allow monitoring of droop events, DVFS transitions, and clock health telemetry. The ACG provides observability into clocking and power delivery network metrics. Users can aggregate metrics such as instantaneous clock changes, lock behavior for environmental impact, and average clock frequency.

Support for real-world operation

The ACG delivers the fastest frequency shift (two cycle response) available, allowing for fast and reliable droop mitigation for varying workloads and environments. The solution also features a programmable ramp rate (in-test and in-field) to safely recover from a voltage droop/glitch and avoid potential ringing on the PDN. Droop parameters can be obtained in mission mode and during post-silicon bring-up. Configuration settings such as droop and DVFS set points can be adjusted, in test and mission mode, per module to address various design objectives and architectures.

The following figure shows a sequence of droop-related events:

• A voltage droop/glitch causes a rapid transition of the clock frequency to the safety frequency
• The safety frequency is maintained for a programmable Tsafety period
• The clock frequency ramps to the programmable frequency F1
• When it is clear that voltage has recovered, the frequency will return to the original F0

The ACG is a key part of an overall feature-rich silicon lifecycle management (SLM) system, ranging from manufacturing all the way to mission mode operation in the field. The ACG provides ultra-fast adaptive clocking, extensive programmability to address varied use cases, architectures and workloads, and observability to allow monitoring of droop events, DVFS transitions, and clock health telemetry. The ACG reads out through its APB interface its comprehensive telemetry, which can be integrated into an SLM solution.

A single clock for large, heterogeneous SoCs creates integration complexities such as full-SoC routing and localized DVFS and droop/glitch mitigation enablement. Design teams can use the ACG for distributed clocking to tune their performance needs per processor type or workload. Silicon changes over time, which means that critical timing paths can morph, altering setup and hold constraints that could lead to system failures. Users can reprogram the ACG after deployment to address the effects of aging circuitry.

Summary

The ACG is delivered as soft (synthesizable) IP for flexible deployment into the user’s process, cell library, and DFT methodology. This makes the IP intrinsically flexible and area efficient. Converting traditionally analog functions into the digital domain enables the development of feature-rich digital IP that is synthesizable and observable. Because it is soft IP, the ACG scales down in size in advanced geometries easily, allowing for inclusion of multiple PLLs, something that is not possible with traditional analog PLLs.

With proven process portability and minimal area footprint, the ACG IP is ideally suited for large-scale distribution within SoCs. As part the Synopsys SLM IP portfolio, the ACG easily integrates with other parts of a complete SLM solution. Clocking flexibility, programmability, DVFS support, and droop mitigation are available today within a single IP. For more information see https://www.synopsys.com/solutions/silicon-lifecycle-management/functional-monitors/advanced-clock-generator-ip.html.