tag: dynamic voltage and frequency scaling

Robust Dynamic Voltage Droop Mitigation And Power Management
By Graham Woods - 13 Jan, 2026 - Comments: 1

Power management is one of the keys for developing successful semiconductors products. There are virtually no applications for which power consumption is not a concern. Many creative solutions have been developed to reduce and manage power. Making these schemes work robustly in real-world conditions can be a challenge. This post considers widely used methods—voltage droop/glitch detection and... » read more

Thermal Sensing Headache Finally Over For 2nm And Beyond
By Nir Sever - 11 Nov, 2025 - Comments: 0

Effective thermal management is crucial to prevent overheating and optimize performance in modern SoCs. Inadequate temperature control due to inaccurate thermal sensing compromises power management, reliability, processing speed, and lifespan, leading to issues like electromigration, hot carrier injection, and even thermal runaway. Unfortunately, precise thermal monitoring reached an inflect... » read more

Critical Optimization Factors For GenAI Chipmakers
By Alex Burlak - 14 Oct, 2025 - Comments: 0

Today’s GenAI arms race is fought with novel chip architectures and packaging. Specialized hardware designs are proliferating in the form of GPUs, TPUs, NPUs, and more, all tuned for parallelism and matrix-heavy AI math. In this hyper-competitive landscape, chip vendors scramble to differentiate their products on multiple fronts. They promise some mix of better performance, efficiency, or ... » read more

Issues In Calculating Glitch Power
By Ed Sperling - 11 Oct, 2023 - Comments: 0

The amount of power consumed by redundant non-functional toggles, or glitch power, can be as high as 35% of total power consumption in a design. What can be done about that? Godwin Maben, low-power architect and scientist at Synopsys, takes a deep dive into the causes of glitch, how it is affected by new process nodes and heterogeneous integration, and the impact of different workloads, higher ... » read more

Design For Reliability
By Brian Bailey - 15 Feb, 2021 - Comments: 1

Circuit aging is emerging as a mandatory design concern across a swath of end markets, particularly in markets where advanced-node chips are expected to last for more than a few years. Some chipmakers view this as a competitive opportunity, but others are unsure we fully understand how those devices will age. Aging is the latest in a long list of issues being pushed further left in the desig... » read more

Designing Low Energy Chips And Systems
By Ann Mutschler - 01 Feb, 2021 - Comments: 1

Energy optimization is beginning to shift left as design teams begin examining new ways to boost the performance of devices without impacting battery life or ratcheting up electricity costs. Unlike power optimization, where a skilled engineering team may reduce power by 1% to 5%, energy efficiency may be able to cut effective power in half. But those gains require a significant rethinking of... » read more

Is DVFS Worth The Effort?
By Brian Bailey - 10 Sep, 2020 - Comments: 2

Almost all designs have become power-aware and are being forced to consider every power saving technique, but not all of them are yielding the expected results. Moreover, they can add significant complexity into designs, increasing the time it takes to get to tapeout and boosting up the cost. Dynamic voltage and frequency scaling (DVFS) is one such power and energy saving technique now being... » read more

Managing Power Dynamically
By Ann Mutschler - 18 Dec, 2019 - Comments: 1

Design teams are beginning to consider dynamic power management techniques as a way of pushing the limits on performance and low power, leveraging approaches that were sidelined in the past because they were considered too difficult to deploy. Dynamic voltage and frequency scaling (DVFS), in particular, has resurfaced as a useful approach. Originally intended to dynamically balance performan... » read more

Variation In Low-Power FinFET Designs
By Ann Mutschler - 30 Aug, 2018 - Comments: 1

One of the biggest advantages of moving to the a leading edge process node is ultra-low voltage operation, where devices can achieve better performance using less power. But the latest generation process nodes also introduce a number of new challenges due to increased variation that can affect everything from signal integrity to manufacturing yield. While variation is generally well understo... » read more

What Happened To UPF?
By Brian Bailey - 16 Apr, 2018 - Comments: 1

Two years ago there was a lot of excitement, both within the industry and the standards communities, about rapid advancements that were being made around low-power design, languages and methodologies. Since then, everything has gone quiet. What happened? At the time, it was reported that the [gettech id="31043" comment="IEEE 1801"] committee was the largest active committee within the IEEE. ... » read more

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