The Challenges Of Working With Photonics

From curvilinear designs to thermal vulnerabilities, what engineers need to know about the advantages and disadvantages of photonics.


Experts at the Table: Semiconductor Engineering sat down to talk about where photonics is most useful — and most vulnerable — with James Pond, fellow at Ansys; Gilles Lamant, distinguished engineer at Cadence; and Mitch Heins, business development manager for photonic solutions at Synopsys. What follows are excerpts of that conversation. To view part one of this discussion, click here.

L-R: Ansys’ Pond, Cadence’s Lamant, Synopsys’ Heins

SE: What will be the domains and the form factors for photonics?

Pond: With the Lumerical tools at Ansys, we deal with photonics more broadly. If I take out my cell phone today, it’s completely full of photonic devices. I’ve got a display, which is very challenging to make. I’ve got all kinds of cameras, such as time-of-flight cameras. I may have VCSELs arrays for facial recognition, so there are a lot of photonics already in our phones. The question is, ‘Is it going to be integrated photonics or silicon photonics?’ I see less need there, than in some of the compute-for-AI things in data centers, where connecting GPUs for high-bandwidth, low power communication is key. It’s not so easy to see right now where that type of optical interconnect would fit onto a cell phone.

Heins: One example of a change in form factor enabled by photonics is lidar. You used to see lidar-equipped cars drive around with what I call the ‘Kentucky Fried Chicken bucket’ on top. Now it’s all solid-state, built into the frame of the car. They care about SWaP (size, weight, and power).

Pond: And cost.

Heins: Exactly. Anytime you have things that are cost-sensitive, integration is a good thing. It also improves your reliability. Additionally, there is Industry 4.0, which is the idea that sensors are going in everywhere in our manufacturing processes. In semiconductors, we’re used to it because it’s quite a complex process. But there are a lot of manufacturing processes that could benefit from sensing. Pipelines are a great example. You’re looking for gas leaks. Is propane coming out, or some other kind of nasty substance that you don’t want floating in the air? All these things can be sensed through sensors that are built with photonics, so photonics could easily end up in those kinds of applications, as well.

Lamant: If you extend the thinking past the PIC (photonic integrated circuit), there are plenty of other applications of photonics, such as in aeronautics manufacturing for examining the wings of an airplane. Or for earthquake detection, you can place a fiber and measure the stress on the fiber in different places. Place a pipe, and the light that comes back gives you information. And if it doesn’t come back, that’s also information. It could mean the pipeline is broken or there’s tension because of an earthquake. You can measure that tension as it’s on the way.

We’re starting to see people doing a lot more photonic-based measurements on surfaces and meta-lenses. At our recent photonics event, a company called Neurophos showed their inference technology. It doesn’t fit on a phone. The way the information is put onto it is actually some discreet optic, but their metasurface is really efficient at processing everything.

All these ideas go back to the question of when we will see it. If you see it in your watch or another device within 10 years, that would be fabulous. Meanwhile, datacom actually has funding. Fabs are opening lines — not small lines, but big lines — with big wafers that are made with good yield, reliable production. It’s not the little fab in a little corner of a lab. We have the fabs investing, and this is all funded by the HPC datacom. But it actually has the side effect of enabling all that innovation, because the fabs want to keep full. Still, applications like sensors and photonics chips are challenging, because developers need variation, and the fabs are not really happy to do variations. They would prefer a standard process with high-yielding, well-calibrated everything. Nevertheless, the fact that the fabs are now opening lines for silicon photonic is a tremendous advantage. It will pull innovation in many other areas because it makes the technology reliably available with good production processes, rather than one device in a lab.

SE: As the foundries are starting to work with curvilinear masks, what is this going to mean for photonics, especially photonics EDA?

Lamant: At 2nm or below, they are naturally manufactured with light in a curvilinear manner. It actually takes a lot of effort to force them to have corners. In the industry right now, people are beginning to ask, ‘What if we actually manufacture them curvilinear?’ There are a few startups that are working on that concept. So curvilinear is actually very often seen. It’s the natural way. The Manhattan way is the non-natural way, and the hard way to do things. If we were lucky enough to find a way to do curvilinear naturally, the challenge is maybe not on the foundry. It’s on the DRC rules, and making sure you can design for it. It’s very hard to extract parasitics on the curvilinear shape. But make that mind shift, and then it’s not that hard for foundries to do curvilinear. It’s actually a lot harder for them to maintain Manhattan.

Fig. 1: Curvlinear shapes in photonics design. Source: Cadence

Heins: A problem we have right now is we, as the semiconductor industry, have worked to optimize our manufacturing processes to try to get to Manhattan-style shapes. A good example in lithography is we set up the scanners that do the printing of the wafers with all sorts of illuminations that are meant to essentially pattern in one direction or the other. If you have something that’s curvilinear, you have to go back and start deciding if you want that kind of illumination. Would it be better to go back to something like an annular illuminator, with a little bit better coverage at unexpected angles?

It’s sort of a good news/bad news situation. A lot of these feature sizes that we’re talking about are quite large, because they’re constrained by the wavelength of the light. We’re talking about things that are in microns, as opposed to nanometers. Typically, when we think patterning issues, it’s extremely small things where we tend to have problems, but everything you pattern with a corner will tend to round out in the process, both from the litho and from the etch, the whole process basically.

In some ways it’s easier because they’re bigger. In other ways, it’s more difficult because we’re sensitive to very small perturbations or shifts in the actual waveguides and the patterns we make. Small things, like line edge roughness in a waveguide, can act like a filter. It can actually filter out certain wavelengths or cause interference or reflections that cause interference. In that regard, sometimes the process itself can also smooth those hard edges out, which helps us. One hand takes, the other hand gives back. It’s an interesting problem.

Pond: Photonics has always been curvilinear. We can’t deal with Manhattan shapes at all. You can’t have a waveguide that turns a right-angled corner. But as the others have said, the scales are quite large in photonics. We’re not talking about advanced nodes. For a lot of the issues around things like the sidewall roughness, we’re getting the precise distance between two waveguides that act as a coupler so light can move slowly from one to the other. Those things are very important, but they often involve a lot of process work and tuning the process, which has been happening. I’m not sure the curvilinear masks, per se, would have anywhere near the same impact on photonics as they may have on other areas of EDA.

Lamant: In the most advanced CMOS, line-edge roughness is a problem for polygate transistors, and the fabs are leveraging the know-how and the technology for doing those things. This reuse of the silicon CMOS knowledge helps photonics tremendously.

SE: If something gets hot enough, the wavelength can actually change. Could that become a problem, given the thermal issues at advanced nodes?

Lamant: Photonics uses thermal as one of the main ways to tune its own functionality. Thermal is a super-important parameter, whether it’s the general temperature around you, whether it’s tuning one device. Consider thermal crosstalk, when you have two devices that are close to each other in photonics, and then, finally, the temperatures are horribly high. Some of those devices go to 300ºC. Think about what that does to the electronics next to it, in terms of the device’s aging, the conductors, the EMIR. Thermal is absolutely a big challenge for photonics. They are trying to make thermally stable phase actuators. I see that in a lot of presentations. They tell you, as long as you don’t vary too much, they are going to be fairly stable. Still, it is definitely a big challenge.

Pond: A 1° shift is enough to completely de-tune a ring modulator or something like that, so it’s very small changes. Typically, we deal with this by actively tuning with heaters to keep everything aligned — all the wavelength channels, and so on. Then the question becomes, how much power do you need to do all that tuning, and how efficient is it? Can you lay things out in such a way that you ensure that you minimize the amount of power that has to be consumed for that type of tuning?

SE: If you’ve got a hybrid, 3D-type chip in which the layers aren’t dissipating heat well, what’s that going to do to the photonics part of the device?

Heins: You have to design for it. You have to design ways to dissipate the heat in a predictable fashion, and then you have to look at how you place things, so that you don’t create hotspots. I used to worry about a hot ASIC sitting on top, de-tuning my photonics. But if you look at the size, the photonics devices are big compared to something like an N5 process. If you put a big heater on top of the photonic device to tune it, and it happens to be smack up against the electronics, you could have literally thousands of transistors that are being impacted by that one big heat source. You have to pay close attention to how you’re going to stack this thing. It makes a big difference, and you have to have tools and methodologies to analyze, and then to do something about it.

Pond: It’s a challenging design problem, because it’s not just the temperature itself. It’s more often changes in temperatures. Modulators for light are often built with an interference method where you have two paths of light. Thus, the challenge isn’t so much that the temperature of the whole chip changes. It’s that the temperature might change in one path compared to the other path, which creates a big problem. You might be able to take 40° temperature rise without a problem, but if you have a 2° difference between those two paths, that’s a big problem.

Lamant: Designing for it means you need to have tools for analyzing it so you can understand what’s happening within the device. There is an ambient one, which is kind of a static one, and then there is a crosstalk one. Those two become dynamic, they change with time. We use it to tune and to make sure, for example, a ring stays on its center frequency. This is one of the really challenging areas for the EDA tool, not only within the photonic chip, but also the photonic chip in a system with everything that happens around it.

Read part one of the discussion:
Photonics: The Former And Future Solution
Twenty-five years ago, photonics was supposed to be the future of high technology. Has that future finally arrived?

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