Knowledge Center ➜ Entities

Synopsys, Inc.

Broad-line supplier of EDA, IP and software testing tools.
popularity

Description

Synopsys is the largest of the Big Three EDA suppliers by revenue and a major supplier of semiconductor IP.

Founded in 1986, Synopsys develops a complete flow of EDA software, from initial design and system modeling through verification and design for manufacturability. The company also provides tools for early software prototyping and virtualization, and for determining the integrity of software that runs on hardware across a variety of vertical markets. It also develops tools for optical communication and TCAD, and IP ranging from standard interfaces to memory controllers and audio subsystems. Target markets are IoT, including wearables and smart medical devices, automotive/autonomous vehicles, and security.

The company’s license structure ranges from renewable TSLs to term licenses and perpetual licenses.

Synopsys also offers design consulting services and cloud-based services. It is the first EDA company to cross the $2 billion revenue threshold.

Executive Insight: Aart de Geus
Synopsys’ chairman and co-CEO looks into the future of Moore’s Law, security, the Internet of Smart Everything, and new opportunities around software.

  • HQ: Mountain View, CA, USA
  • Web: URL
  • Other names: Synopsys. Synopsys, Inc. used to be known as Optimal Solutions, Inc. until 1987. In 1987, Optimal Solutions changed it’s name to Synopsys.
  • Type: Company

Invention:

Founding: Synopsys, Inc. founded:

Acquisitions:
Synopsys, Inc. acquired:

Subsidiary:

Deprecation of:

  • Synopsys, Inc. used to be known as Optimal Solutions, Inc. until 1987. In 1987, Optimal Solutions changed its name to Synopsys.

Synopsys Logo

  • Type: Company

Multimedia

Changes And Challenges In Auto MCUs

Multimedia

Very Short Reach SerDes In Data Centers

Multimedia

What To Do About Electrostatic Discharge

Multimedia

Designing Chips For Outer Space

Multimedia

DSP Techniques For High-Speed SerDes

Multimedia

Issues In Calculating Glitch Power

Multimedia

Die-To-Die Security

Multimedia

Multi-Die Integration

Multimedia

Challenges In Ramping New Manufacturing Processes

Multimedia

Speeding Up Design Closure

Multimedia

Using AI To Close Coverage Gaps

Multimedia

RTL Restructuring Issues

Multimedia

Changes In Memory Design

Multimedia

The Impact Of ML On Chip Design

Multimedia

Challenges In Writing SDC Constraints

Multimedia

100G Ethernet At The Edge

Multimedia

Co Packaged Optics In The Data Center

Multimedia

The Ethernet Evolution

Multimedia

1.6 Tb/s Ethernet Challenges

Multimedia

Next Gen SerDes Roadmap

Multimedia

Shifting Auto Architectures

Multimedia

Next Gen Design Challenges

Multimedia

Data Overload In The Data Center

Multimedia

IP Safe Enough To Use In Cars

Multimedia

Silicon Lifecycle Management

Multimedia

112G SerDes Reliability

Multimedia

Memory Access In AI Systems

Multimedia

Different Types Of AI Hardware

Multimedia

High-Speed SerDes At 7/5nm

Multimedia

DDR PHY Training

Multimedia

Building A Safety Verification Flow

Multimedia

Timing Closure At 7/5nm

Multimedia

Enterprise-Class DRAM Reliability

Multimedia

Fusing Implementation And Verification

Multimedia

Hybrid Prototyping

Multimedia

Automotive Chip Design Workflow

Multimedia

Tradeoffs In Embedded Vision SoCs

Multimedia

Using Static Analysis For Functional Safety

Multimedia

Distributed Design Implementation

Multimedia

Die-To-Die Connectivity

Multimedia

The New CXL Standard

Multimedia

Visually Assisted Layout In Custom Design

Multimedia

Compressing High-Bandwidth Video

Multimedia

Signoff-Compatible CDC

Multimedia

Holes In AI Security

Multimedia

Analog Fault Simulation

Multimedia

New Challenges For Data Centers

Multimedia

Automotive System Design

Multimedia

Verification at 7/5nm

Multimedia

Safety Critical Design In Automotive

Multimedia

Debug Changes At Advanced Node

Multimedia

Designing An AI SoC

Multimedia

Reverse Debug

Multimedia

Designing Networking Chips

Multimedia

Boosting Analog Reliability

Multimedia

Formal Signoff

Multimedia

Making Sense Of DRAM

Multimedia

Formal Datapath Verification

Multimedia

Thermal Impact On Reliability At 7/5nm

Multimedia

UPF-Aware Clock-Domain Crossing

Multimedia

Changing The Design Flow

Multimedia

M2M Network Impact

Multimedia

In-Design Power Rail Analysis

Multimedia

Designing In The Cloud

Multimedia

Emulation-Driven Implementation

Multimedia

On-Chip Variation

Multimedia

5/3nm Parasitics

Multimedia

Writing Software (2016)