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Co-Design Automation, Inc.

Created Superlog, a foundation language for SystemVerilog


Co-Design created the Superlog language, based on the Verilog hardware description language, extending its capabilities into verification and system design. Parts of Superlog became incorporated into the SystemVerilog language standardized by Accellera in 2003. The company utilized this technology in two products, SYSTEMSIM, a simulator targeted at system design issues, and SYSTEMEX, a system to implementation design extractor.