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Manufacturing, Packaging & Materials

Top Stories

Gearing Up For High-NA EUV

High-NA EUV scanners could cost nearly $320M each, but big foundries already are lining up.

Progress On General-Purpose Quantum Computers

Repeatable results and behavior, but still plenty of issues to solve.

What’s Next For Transistors And Chiplets

Imec's SVP drills down into GAA FETs, interconnects, chiplets, and 3D packaging.

Fan-Out And Packaging Challenges

Experts at the Table: Wafer-level and panel-level approaches, packaging economics, and the need for new materials.

The Silicon Carbide Race Begins

As SiC moves to higher voltages, BEV users get faster charging, extended range, and lower system costs

Gearing Up For Next-Gen Power Semis

Aluminum nitride, diamond semiconductors, gallium oxide and vertical GaN are all being readied, each with its own pros and cons.

Nudging 2D semiconductors forward

Stacked nanosheet transistors promise to extend silicon’s reign beyond the finFET era.

Challenges With Chiplets And Packaging

Experts at the Table: The impact of optics, copper hybrid bonding, more standardized interconnects, and many other technologies under development.

How Chips Will Change Health Care

Imec's chief strategy officer explains how ICs are being used today, and how they will impact medical treatment in the future.

Inside Intel’s Ambitious Roadmap

Five process nodes in four years, high-NA EUV, 3D-ICs, chiplets, hybrid bonding, and more.

More Top Stories »



Round Tables

Fan-Out And Packaging Challenges

Experts at the Table: Wafer-level and panel-level approaches, packaging economics, and the need for new materials.

Challenges With Chiplets And Packaging

Experts at the Table: The impact of optics, copper hybrid bonding, more standardized interconnects, and many other technologies under development.

Current And Future Packaging Trends

Experts at the Table: Rising costs and the physical limits of reticles is forcing more companies to examine alternatives to shrinking geometries.

What’s Next In Fab Tool Technologies?

Experts at the Table: Semiconductor Engineering sat down to discuss extreme ultraviolet (EUV) lithography and other next-generation fab technologie...

Applications, Challenges For Using AI In Fabs

Deep learning and digital twins can help identify patterns and ultimately may be able to fix any problems that arise, but it will take awhile.

More Roundtables »



Multimedia

Open Cavity Plastic Packaging

Dealing with obsolescence through retrofitting.

What’s Changing In DRAM

The impact of shrinking features on memory.

Changing The Rules For Chip Scaling

The potential impact of curvilinear photomask capabilities on transistor density.

Virtual Fabrication At 7/5/3nm

Using data from multiple sources to improve yield.

Challenges At 3/2nm

New structures, processes and yield/performance issues.

More Multimedia »



See All Posts in Manufacturing Packaging and Materials »

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Cost-effective solutions for low to mid-volume packaging.
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Knowledge Centers
Entities, people and technologies explored


  Trending Articles

Software-Hardware Co-Design Becomes Real

Automatic mapping of software onto existing hardware, or using software to drive hardware design, are highly desired but very difficult.

HBM3: Big Impact On Chip Design

New levels of system performance bring new tradeoffs.

PCB And IC Technologies Meet In The Middle

Surface mount technology is changing in some surprising ways.

Inspecting, Testing, And Measuring SiC

Demand for solutions is booming, but the technology is just beginning to gain its footing.

Fan-Out And Packaging Challenges

Experts at the Table: Wafer-level and panel-level approaches, packaging economics, and the need for new materials.