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Manufacturing, Packaging & Materials

Top Stories

The Quest For Curvilinear Photomasks
Why this technology is vital for chip scaling, and what problems still need to be resolved.
Published on April 15th,  2021 by Mark LaPedus

Making Chip Packaging More Reliable
Challenges rise for both advanced packages and for new innovations in older technologies.
Published on April 15th,  2021 by Mark LaPedus

Going Vertical With GaN Devices
Technology may finally be on the verge of commercialization.
Published on April 15th,  2021 by Katherine Derbyshire

Applications, Challenges For Using AI In Fabs
Deep learning and digital twins can help identify patterns and ultimately may be able to fix any problems that arise, but it will take awhile.
Published on April 14th,  2021 by Mark LaPedus

What Goes Wrong In Advanced Packages
More heterogeneous designs and packaging options add challenges across the supply chain, from design to manufacturing and into the field.
Published on March 24th,  2021 by Ed Sperling

EUV Pellicles Finally Ready
Yield rises with mask protection; multiple sources will likely reduce costs.
Published on March 22nd,  2021 by Mark LaPedus

Chasing After Carbon Nanotube FETs
CNTs promise big performance improvements, but achieving consistency and replacing incumbent technologies will be difficult.
Published on March 18th,  2021 by Mark LaPedus

The Future Of Transistors And IC Architectures
The more compute power, the better. But what's the best way to get there?
Published on March 18th,  2021 by Mark LaPedus

IC Materials For Extreme Conditions
NASA looks to SiC and diamond for Venus electronics.
Published on March 18th,  2021 by Katherine Derbyshire

Brazil Paves New Semiconductor Path
After failing in the fab race, the country has started focusing on less capital-intensive segments.
Published on February 22nd,  2021 by Mark LaPedus

More Top Stories »



Round Tables

Applications, Challenges For Using AI In Fabs
Deep learning and digital twins can help identify patterns and ultimately may be able to fix any problems that arise, but it will take awhile.
Published on April 14th,  2021 by Mark LaPedus

The Future Of Transistors And IC Architectures
The more compute power, the better. But what's the best way to get there?
Published on March 18th,  2021 by Mark LaPedus

AI And High-NA EUV At 3/2/1nm
EUV double patterning likely at 3nm; what comes after that is uncertain.
Published on December 16th,  2020 by Mark LaPedus

Challenges Linger For EUV
Experts at the Table: The challenges of putting EUV into production, and why DRAM will require advanced litho in the future.
Published on November 11th,  2020 by Mark LaPedus

Mask/Lithography Issues For Mature Nodes
Experts at the Table: Spare parts are scarce for some tools and they don't do everything, but they are nearly free to operate. That limits purchase...
Published on October 22nd,  2020 by Mark LaPedus

More Roundtables »



Multimedia

Changing The Rules For Chip Scaling
The potential impact of curvilinear photomask capabilities on transistor density.
Published on March 10th,  2021 by Ed Sperling

Virtual Fabrication At 7/5/3nm
Using data from multiple sources to improve yield.
Published on October 23rd,  2020 by Ed Sperling

Challenges At 3/2nm
New structures, processes and yield/performance issues.
Published on September 15th,  2020 by Ed Sperling

Using Digital Twins And DL In Lithography
How to speed up manufacturing with inverse lithography technology with complex curvilinear data.
Published on November 21st,  2019 by Ed Sperling

Curvilinear Full-Chip ILT
Why inverse lithography technology has finally come of age.
Published on October 17th,  2019 by Ed Sperling

More Multimedia »



See All Posts in Manufacturing Packaging and Materials »

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