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The Drive Toward Zero Defects


The automotive semiconductor market has doubled twice in the past 20 years. But the next doubling will be even faster. While short-term results may vary, it is certain that auto semis will be much larger 10-20 years from now. Today, a gas-powered car has ~$400 of semiconductor content whereas the Tesla Model 3 with an electric powertrain and Advanced Driver Assist System (ADAS) has >4... » read more

Challenges For Achieving Automotive Grade 1/0 Reliability In FCBGA and fcCSP Packages


As the quantity, complexity, and functions of electronic devices in automobiles increase, understanding and characterizing package reliability is of significant concern and importance. The Automotive Electronics Council (AEC) Q-100 specification for Grade 1 and 0 reliability introduces unique challenges as thermal cycling (TC) and high temperature storage (HTS) requirements increase. Additional... » read more

Wirebond IC Substrates: Challenges Ahead


Substrate suppliers are slashing capacity allocated to wirebond IC substrates. We hear about "limited tenting capacity," "no support for EBS designs," and requests for "conversion to etchback" designs. What does all this mean? Let's start with "Line" and "Space." "Line" is the width of a trace on a substrate and "Space" is the distance between the two traces. For wirebond packages such a... » read more

Thermal Management Implications For Heterogeneous Integrated Packaging


As the semiconductor industry reaches lower process nodes, silicon designers struggle to have Moore's Law produce the results achieved in earlier generations. Increasing the die size in a monolithic system on chip (SoC) designs is no longer economically viable. The breakdown of monolithic SoCs into specialized chips, referred to as chiplets, presents significant benefits in terms of cost, yield... » read more

Thin Quad Die Package (QDP) Development


In the world of solid-state memory fabs, bits per mm2 rule. In the memory packaging market, mm2 of silicon per a given package thickness is the defining feature. Both the memory architecture of the wafer and the package technology take advantage of 3D structures to achieve best in class bit density. In the case of the wafer fab, 3D NAND and other technologies are pushing the envelope to meet ev... » read more

Design Process And Methodology For Achieving High-Volume Production Quality For HDFO Packaging


Unlike the traditional system on chip (SoC) design process, which has fully qualified verification methods embodied in the form of process design kits (PDKs), chip design companies and outsourced semiconductor assembly and test (OSAT) suppliers have typically had no integrated circuit (IC) package co-design sign-off verification process to help ensure that an IC package will meet manufacturabil... » read more

Achieving Success In Automotive Leadframe Packages


The growth of semiconductor content in automotive applications has been accelerating. This growth drives all families of semiconductor packaging in all regions. The growth is happening in the latest advanced, laminate-based packages using flip chip interconnect as well as the venerable leadframe packages using wirebond interconnect. The automotive market consumes micro-electromechanical systems... » read more

The New Technology Solutions For Advanced SiP Devices


For many years, System-in-Package (SiP) technology has been a focus for semiconductor packaging to address the ongoing market trend of system integration and size reduction. Today’s increased complexity and higher package density for SiP devices has driven the development of new packaging technologies. In response, compartmental shield technology makes it possible to put several functions int... » read more

The New Technology Solutions For Advanced SiP Devices


For many years, system-in-package (SiP) technology has been a focus for semiconductor packaging to address the ongoing market trend of system integration and size reduction. Today’s increased complexity and higher package density for SiP devices has driven the development of new packaging technologies. In response, compartmental shield technology makes it possible to put several functions int... » read more

Empowering RF Front End Cellular Innovations With DSMBGA


With the introduction of 5G, cellular frequency bands have increased considerably, requiring innovative solutions for the packaging of RF front-end modules for smartphones and other 5G-enabled devices. Double-sided, molded ball grid array (DSMBGA) is a prime example of such solutions. “With our DSMBGA platform, we’ve established a preferred advanced packaging solution for this domain,”... » read more

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