How To Build Billions of Bumps

By Bryon Moyer - 18 Jun, 2026 - Comments: 0

Key Takeaways: Hybrid bonding can result in a package containing billions (and eventually trillions) of connections. Building that many connections successfully requires extreme process uniformity across a wafer. Inspection isn’t practical, and test benefits from internal test mechanisms. Hybrid bonding allows unprecedented signal pitch, but fully populating dies and inter... » read more

PCIe Benefits From AI, Despite Scaling Protocols

By Bryon Moyer - 10 Jun, 2026 - Comments: 0

Key takeaways: PCIe remains a critical technology for non-AI processing. For AI, PCIe will be strengthened by scale-out, agentic AI, and even some scale-up. CXL is seeing uptake, and some even think it could participate in AI processing. PCIe has been the go-to network for most data traffic moving from a processor to devices located elsewhere, which is also what the new data... » read more

With Chiplets, What Role Does Economics Play?

By Bryon Moyer - 21 May, 2026 - Comments: 1

Key Takeaways: For the data center, chiplet economics matter, but they’re not a primary decision-driver. With the exception of processor families, chiplets cannot address consumer markets today, where economics dominate. If a chiplet marketplace materializes, the economics may be friendlier because chiplets will have multiple customers and applications. Chiplets are notori... » read more

Flash Getting Stacked High-Bandwidth Version

By Bryon Moyer - 14 May, 2026 - Comments: 1

Key takeaways: A new HBF 3D flash stack is similar to HBM for use in AI processing. HBF capacity will be much higher, allowing static storage of AI model weights, with optimized read speed. Samples are due out later this year, with accelerators featuring it coming out next year. AI inference using modern models requires billions of parameters, and moving them to where they c... » read more

Chiplet Standards Aim For Plug-n-Play

By Bryon Moyer - 16 Apr, 2026 - Comments: 0

Key Takeaways Die-to-die chiplet standards are only the beginning. Many more standards are necessary for a chiplet marketplace. A number of such standards have either had initial versions released or are in progress. Existing work covers packaging, a system architecture, various design kits, a universal link layer, and updates to BoW. Today’s chiplets exist in silos. In a ... » read more

DRAM’s Whac‑A‑Mole Security Crisis

By Bryon Moyer - 09 Apr, 2026 - Comments: 0

Key takeaways: Rowhammer remains a DRAM security threat, while Rowpress has increasingly become a related threat. New commands issued by the memory controller can help manage refreshes, but they’re not a perfect solution. A smaller, vertical DRAM cell may eliminate the problem, but it’s years away. Rowhammer has been a persistent DRAM issue across several memory generati... » read more

Liquid Cooling Drives Other Localized Cooling

By Bryon Moyer - 19 Mar, 2026 - Comments: 0

Key Takeaways: When converting from air to liquid cooling, components without liquid may become too hot. An entire board or system must undergo thermal analysis to ensure that any components that were once cool enough remain cool. Alternative cooling techniques may be needed for components without liquid cooling. Liquid cooling is proving effective at cooling high-power chip... » read more

Scale Up, Scale Out Get a New Partner

By Bryon Moyer - 12 Mar, 2026 - Comments: 0

Key Takeaways: Three AI data center scaling strategies are scale-up, scale-out, and scale-across. Scale-up is within a rack; scale-out is between racks; scale-across is between data centers. Each of the three uses a different interconnect strategy to optimize either latency or jitter. As today’s data center workloads — especially for AI and HPC — outgrow the physical, ... » read more

Laser Arrays May Simplify Co-Packaged Optics

By Bryon Moyer - 19 Feb, 2026 - Comments: 0

Key Takeaways Moving photonic ICs into the same package as silicon helps improve performance, but lasers remain outside. A new monolithic laser array allows hundreds of colors, each individually software-tunable New options are being turned into products, which could help commercialize CPO. The move to co-packaged optics (CPO) holds the promise of putting photonic ICs (PICs)... » read more

UCIe’s Major Technical Components Are Now In Place

By Bryon Moyer - 12 Feb, 2026 - Comments: 0

Key Takeaways UCIe 3.0 doubles bandwidth and enhances manageability, addressing new use cases and following an annual update cycle since 2023. The growing demand for chiplet-based architectures in AI data centers is driven by the limitations of monolithic chips, making inter-chiplet communication and connectivity crucial. While UCIe was initially seen as feature-heavy, many of its ma... » read more

← Older posts