Author's Latest Posts


Liquid Cooling Gains Traction In Data Centers


All electronics generate heat, and that heat must be removed to ensure those electronics don’t overheat. Moving air has been the predominant approach for decades, with liquid cooling limited to particularly intense computing workloads, largely in the supercomputing domain. With the rise in AI, data-center power density has grown to the point where liquid cooling is now seeing a larger buil... » read more

HBM4 Sticks With Microbumps, Postponing Hybrid Bonding


The next generation of high-bandwidth memory, HBM4, was widely expected to require hybrid bonding to unlock a 16-high memory stack. A JEDEC move made that unnecessary with this generation, but it’s merely a postponement, not a cancellation. HBM has been in high demand for AI in data centers — especially for training. Data movement dominates energy consumption, and high-bandwidth memories... » read more

What’s Next for 2.5D Packaging?


Interposers and bridges, two of the key elements for interconnecting multiple chips and chiplets in an advanced package, are undergoing fundamental changes in how they're built and assembled. Interposers are becoming thicker and more complex, while bridges are being used to reduce the assembled cost. Both efforts are facing new challenges. Interposers are effectively platforms on which mu... » read more

Chiplets Vs. Soft IP: Different In Almost Every Way


Chiplets serve a similar function as the soft IP widely used in chips today, but the similarities end there. While both can speed time to market and enable design teams to focus limited resources where they can best be applied, the implementation, manufacturing, test, and long-term business requirements wrought by a chiplet marketplace would be very different. Soft IP (also known as RTL IP) ... » read more

New Panel Production Efforts Target Interposer Costs


The rising cost of increasingly large interposers is spurring renewed interest in panel-level manufacturing, which for years has hobbled along due to the massive and collective effort required by the chip industry to change formats. Several companies are developing their own processes, although there is currently no commercial production. And a new consortium called Joint3, spearheaded by Ja... » read more

Multiple AI Scale-Up Options Emerge


Artificial intelligence (AI) workloads are very different from those traditionally run inside of data centers, and while the current infrastructure can accommodate those needs, there is a constant demand for higher performance and better power efficiency. It can take months to train a large language model, even with a huge number of processing elements. Typically this involves commandeering ... » read more

Data Centers Boost Voltage For Higher Efficiency


The power architecture used in HPC and AI data centers today is about to undergo a significant change in an effort to boost power efficiency. While voltages at the chip level will remain the same, the voltages leading to those chips will be kept higher for longer distances. This change has broad implications for DC-DC converters. The existing architecture brings AC to each rack, converts it ... » read more

Voltage Regulation Moves Into The Package


Integrated circuits require a variety of voltages and a wide range of currents, typically supplied by voltage regulators. But increasing power density is resulting in higher power delivery losses. Moving those regulators closer to the chips they power can reduce those losses. Co-packaging them holds the most promise, but it comes with challenges. “What people have been talking about, ev... » read more

Coloring Optical Signals For More Bandwidth In Data Centers


Copper cabling has been the workhorse for moving data inside of AI and HPC data centers, but fiber is nipping at its heels. Optics brings three possible bandwidth multipliers — wavelength-division multiplexing (WDM), the use of different modes, and polarization. Each has a role in longer-distance optical links, but the tradeoffs are different in the data center. WDM appears poised to boost... » read more

Reticle Stitching Bumps Up Silicon Interposer Costs


Advanced packaging often relies on silicon interposers to connect chiplets and other components inside a package. The problem is that interposers typically exceed the reticle limit, which adds both complexity and cost. An interposer is essential for 2.5D and 3.5D architectures. As device scaling runs out of steam, chipmakers are decomposing planar SoCs into chiplets and connecting them throu... » read more

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