New Panel Production Efforts Target Interposer Costs

The rising cost of increasingly large interposers is spurring renewed interest in panel-level manufacturing, which for years has hobbled along due to the massive and collective effort required by the chip industry to change formats.

Several companies are developing their own processes, although there is currently no commercial production. And a new consortium called Joint3, spearheaded by Japan’s Resonac, is looking to accelerate those efforts.

How this ultimately will unfold isn’t clear at this point. The magnitude of this shift is daunting. New equipment and processes will be required to manufacture larger interposers, which have a finer line pitch than today’s substrate processes, and all of that will need to be fine-tuned to ensure sufficient yield to warrant these investments.

“It is important to note that high-volume production of panels or organic interposers would require a completely different automatic material handling system (AMHS) and clean-room setup,” said Pax Wang, director for advanced packages at UMC. “This new setup must be capable of integrating both silicon chips and panel-handling processes, starting from cutting round silicon wafers into individual chips through assembling them onto panels with organic interposers.”

And even if this does come to fruition, nothing will happen overnight. Manufacturing equipment still needs to be developed for large rectangular formats, and panel sizes need to be standardized. “There are size limitations for certain equipment,” noted Anshu Bahadur, head of smart manufacturing at SEMI.

Nevertheless, the economic incentive is growing. Interposers are becoming bigger, more essential, and more costly for many applications, and one of the best ways to reduce that cost is to shift from wafers to large rectangular panels. It’s also why Joint3’s membership is growing.

Joint3’s plan is to develop a new pilot line that participants can use to dial in a process, which then can be transferred to production lines. This allows participating companies to leverage the equipment already in place for making substrates. “There are institutes globally, but some are focusing on the front end, some are focusing on the wafer process, and some focus on glass,” said Hidenori Abe, executive director, Electronics Business Headquarters at Resonac. “But no institute is driving a project for large panel-level interposers.”

Squaring a circle
What’s changed over the past few years is the rapid adoption of multi-die assemblies, particularly in AI data centers. Chips and interposers are getting physically bigger, and cost and yield issues are growing with them. With high-performance chips developed at advanced process nodes, it’s difficult enough, although less so given the maximum reticle size limitation. But interposers tend to be several times larger than the chips, making their cost profile more challenging.

Fortunately, not all interposers need to be silicon-based. Passive interposers have no active circuitry, so they don’t rely on the properties of leading-edge silicon processes the way chips do. That allows for alternative — and less expensive — interposer materials that might not work for chips owing to poor performance. Organic panels and glass are both being considered for use as interposers.

Panels start with a rectangular core of arbitrary shape. There are no circular edges to go to waste. All the material sees productive use. Silicon wafers, in contrast, are round because of the way silicon ingots are grown and sliced. The round shape also facilitates uniform processing inside chambers, but that comes at a price.

Organic panels are completely different, following the general format of printed circuit boards (PCBs), albeit with much more aggressive line/space (L/S) dimensions than a PCB would have. Package substrates are a closer fit, as they need tighter dimensions — as low as 10µm L/S — than PCB tools, which have a L/S capability many times larger.

Leading-edge interposers bring dimensions down to 1µm L/S, which is below what’s possible on a substrate. Further process development is necessary to achieve those dimensions in high-volume production.

But flexibility in size also has stymied adoption in the past. Part of the issue is that no standards exist yet. “The equipment companies keep saying, ‘Because there are no standards on the panel size, it’s very difficult to anticipate where customers are going in terms of building equipment,’” said Mark da Silva, senior director, manufacturing collaborations at SEMI.

Potential customers also voice support without moving forward. “There’s an acceptance challenge,” said SEMI’s Bahadur. “While it has been touted that panels are the next big thing, they haven’t been accepted by end users. Though everybody seems to be excited that panel manufacturing is coming, are they willing to use it? I haven’t seen that.”

While a panel theoretically can be any size, equipment design requires assumptions about the sizes of panels to be processed. Some companies are talking about panels as large as 600 or 700mm on a side, but such projects are developing within individual companies, and the industry hasn’t embraced those sizes.

“People have said there are 600×600mm² panels that they can work on, but there is no panel development kit,” said Bahadur. “So there are various elements holding back panel development.”

Another issue is equipment to handle the panels is lacking. “You need the equivalent of a FOUP [front-opening unified pod],” said da Silva. “You need robots that can handle that panel size.”

Because of this uncertainty, equipment makers have been reluctant to commit to production equipment, and without equipment, there are no production panels. It’s a bit of a chicken-and-egg problem.

Toward a full production process
In addition to panel size, a full production process is necessary. Plenty of isolated projects have focused on different individual elements of a process such as lithography, deposition, etching and cleaning, but more effort is needed to move large panels to production. For example, the Japanese government funded an earlier program, Joint2, that developed isolated process steps but not the complete flow.

In the wake of Joint2 comes Joint3. Notably, this consortium of 27 participants is not government-funded. Most, but not all, are Japanese companies, and most of the non-Japanese players are globally recognizable names.

Fig. 1: Participants in the Joint3 panel program. Source: Resonac

The list of companies joining the consortium offers a glimpse into how many elements are involved in making organic panel-level interposers a reality. “As device complexity and size increase, wafer-based interposers face yield and cost challenges said Poupak Khodabandeh, chief business officer at Brewer Science. “Panel-level manufacturing enables higher throughput, lower cost per interposer, and scalability for AI, HPC, and advanced consumer applications.”

Brewer Science’s role will involve front-end and back-end requirements, combined with advanced polymeric chemistry. “With prototype panel production slated to begin in 2026, Joint3 is a great example of how collaboration can accelerate new packaging architectures and move the industry forward,” Khodabendeh said.

Lam Research, meanwhile, will provide deposition and etch for high-bandwidth memory, AI CPUs, and GPUs. “Joining the Joint3 consortium positions us to help drive advanced substrate technology into the new era,” said a company spokesperson.

“New breakthroughs in chip packaging are critical to achieving increasing levels of performance, energy efficiency, and manufacturability of complex AI silicon, and panel-level interposer packaging holds promise as a cost-effective and adaptable platform,” said Steve Pytel, vice president of product management at Ansys, now part of Synopsys. “Access to Synopsys’ multi-physics simulation, design validation, and virtual prototyping solutions will enable cross-disciplinary collaboration and help consortium partners rigorously validate their concepts and accelerate the delivery of market-ready panel-level interposer technologies.”

Even companies that today are not actively participating in panel-level organic interposers are keeping the door open in case the market picks up steam. UMC, for example, currently has no plans to venture into panel and organic interposer production, and is not a member of the Joint3 consortium. “However, recognizing the ever-evolving market dynamics, UMC has initiated collaboration with ecosystem partners to prepare for potential panel and organic-interposer solutions,” Wang said.

Specs, facilities, and schedule
The Joint3 group is working on 515×510mm² panels. Although that might seem like a strange set of numbers, especially being just off square, it’s the size employed by package-substrate makers. “This is a standard size for the substrate industry,” said Abe. “That means panel-level equipment is ready to support this size.”

That process equipment may require modifications, but it doesn’t need to be designed from scratch. It is, however, a smaller size than some of the other companies are exploring, so the industry will ultimately need to decide how big the panels will be.

One of the challenges the project faces is that while the size matches that of substrates, the line/space requirements do not. “With substrates, we are talking about line/space of 10µm,” said Abe. “But for interposers, we’re talking about below 1µm. So for equipment such as our lithography capability, the level is totally different.”

And with that comes the need for a cleanroom. “If you go to line/space at 5µm, you need a cleanroom, but not the same accuracy as a clean room for chip manufacturing,” said Andy Heinig, department head for efficient electronics at Fraunhofer IIS’ Engineering of Adaptive Systems Division.

“Doing metallization on such large panels with tight tolerance is an issue,” said Bahadur. “They’ve done this in R&D, but achieving very tight tolerances and alignment in production may be difficult. And the interposers crack easily.”

So this panel-level processing straddles the line between traditional packaging, which requires no cleanroom, and silicon processing, which requires incredible cleanliness. As these developments progress, it starts to look more like front-end silicon processing. “We try to use a silicon-processing methodology, whether it’s organic or a glass substrate,” noted Bahadur.

The rectangular panel shape also creates a challenge for some process steps that have been standard with silicon for decades. “Applying materials is a key challenge,” noted Abe. “Liquid materials use a spin-on coating, a well-established process for uniform thickness. But spin-coating over a panel is not so easy, especially for good uniformity.”

Started this year, Joint3 has a few years to run. “We started this activity last August, and this will be a five-year project,” said Abe. The plan is initially to build a new advanced panel-level interposer center (APLIC) in Yuki City, Ibaraki Prefecture north of Tokyo. Interposer sizing will target 8X to 10X reticle sizes, 1µm L/S interconnects, and 5 wiring layers. They also will work on die-embedded interposers with 2µm L/S for silicon bridges.

Fig. 2: The two types of interposers that will be developed at the APLIC. Source: Resonac

A second building, in Kawasaki, is an existing advanced packaging R&D site. It will build packages using interposers created at the APLIC, affixing them to motherboards to evaluate the results.

The standard or just the next step?
While Joint3 may jump-start production of interposers from panels, it is unclear whether the process will become an official or even a de facto standard. The benefit of the sizing used for Joint3 is that equipment exists for that size. That removes one big barrier to progress.

Another advantage is that the project does not involve setting up a high-volume production line. “Our goal is to make better material using this pilot line,” said Abe. “Joint3 is kind of a practice field for us, using that test vehicle so we can brush up on our materials before going to our customers. We will not make a mass production line for those interposers. That’s not our business. That’s our customers’ business.”

Once the project is complete, Joint3 members will gain access to the process. Companies outside the consortium will need to perform their own separate development work.

Will even larger panels succeed the ones Joint3 is developing? Perhaps. If the Joint3 process enters volume production, then customer response should be more evident, and production issues can be addressed at the 515×510mm size before exploring something larger. That removes some of the chicken-and-egg challenge, allowing production at substrate sizes while working on whatever the next step in the process will be.

SEMI also is preparing a white paper on the topic for release toward the end of 2025. “SEMI has a tech community called the advanced packaging and heterogeneous integration (APHI) community,” said da Silva. “The co-chairs are Ravi Mahajan from Intel and Bill Chen from ASE, and the way [forward] right now is to do a call for action on the standards gaps. So SEMI and iNEMI are working on a white paper to understand the standards landscape for some of these efforts. It’s not just about the panel size. It’s about all the infrastructure to support that panel size.”

Presented by an industry consortium, the paper hopefully will reflect directions that the industry desires, whether following the Joint3 path or something else. For now, however, Joint3 appears to be the most promising full-process program.

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