tag: panel-level packaging

Inspection And Metrology Catching Up For High-Density Fan-Out Panel Packaging
By Anne Meixner - 07 Jul, 2026 - Comments: 0

Key Takeaways:  To support AI/HPC devices, high-density fan-out on panels must deliver increased RDL layer count and micropillar height while decreasing the trace and bump/micropillar pitch.   Metrology and inspection steps assist with achieving known-good panel requirements to avoid throwing away expensive chiplets, such as HBM and TPUs.  Optical measurement systems need to acco... » read more

Automated 310mm Panel-Level Packaging to Accelerate AI Innovation: Tech Brief
By ASE - 18 Jun, 2026 - Comments: 0

This shift to panel-level packaging addresses critical industry challenges, including rising interposer sizes and declining wafer-level efficiency. The larger panel format supports higher throughput, reduced cycle time, and lower cost per package, while enabling integration of increasingly complex multi-die architectures. These benefits are especially impactful for AI data center and HPC applic... » read more

Panel-Level Packaging’s Second Wave Meets Engineering Reality
By Gregory Haley - 16 Apr, 2026 - Comments: 0

Key Takeaways Panel-level packaging is arriving not because the engineering is ready, but because wafer-level economics are breaking down. Glass improves the warpage and dimensional stability problems of organic substrates but introduces a different class of failure modes that require materials solutions, not process adjustments. The central challenges of panel-level processing are m... » read more

Advanced Packaging Limits Come Into Focus
By Gregory Haley - 19 Mar, 2026 - Comments: 0

Key Takeaways: Packaging is now a performance variable. Substrate, bonding, and process sequence determine what can be built at scale. Warpage underlies most advanced packaging failures and gets harder to control as package sizes grow. Every proposed solution, such as glass, panel processing, and backside power, solves one problem while creating another. Moore's Law has shif... » read more

Reliability Risks Shift To The Materials Stack
By Gregory Haley - 18 Dec, 2025 - Comments: 0

The semiconductor industry’s push into 3D integration and large-format substrates has fundamentally changed the role of materials in packaging. What were once structural supports and electrical insulators have become critical performance limiters. Modern packages contain far more polymers, adhesives, advanced dielectrics, thermal materials, and composite laminates than previous generations... » read more

Advanced Packaging: Driving Innovation, Performance, And New System Capabilities
By Cassandra Melvin - 18 Dec, 2025 - Comments: 0

Advanced packaging is no longer operating behind the scenes. The technology of advanced packaging is helping to sustain the speed of the semiconductor industry’s improvement in power and performance, even as the Moore’s Law roadmap for wafer-level scaling comes under strain. At the Advanced Packaging Conference during SEMICON Europa 2025 in Munich, global experts examined the growth tr... » read more

New Panel Production Efforts Target Interposer Costs
By Bryon Moyer - 20 Nov, 2025 - Comments: 0

The rising cost of increasingly large interposers is spurring renewed interest in panel-level manufacturing, which for years has hobbled along due to the massive and collective effort required by the chip industry to change formats. Several companies are developing their own processes, although there is currently no commercial production. And a new consortium called Joint3, spearheaded by Ja... » read more

The Opportunities And Challenges Of FOPLP Technology
By Teck Lee - 23 Oct, 2025 - Comments: 0

Artificial intelligence (AI) has emerged as a major catalyst for innovation and advancement. The growing demand for AI computing power is driving heterogeneous integration toward larger packaging sizes, sparking increased interest in Fan-out Panel Level Package (FOPLP) technology. This article explores ASE’s practices and developments in this area, delving into the technical intricacies and e... » read more

Precision Under Pressure: Managing Materials Complexity In Advanced Packaging
By Gregory Haley - 18 Sep, 2025 - Comments: 0

In the race to extend Moore's Law through advanced packaging, the limits of precision are no longer defined solely by lithography. Increasingly, they are dictated by the unpredictable behavior of materials. Semiconductor packaging today is no longer limited to just silicon and copper. It includes an expanding range of polymers, adhesives, dielectrics, exotic metals, along with substrates suc... » read more

Glass Substrates Gain Momentum
By Laura Peters - 18 Sep, 2025 - Comments: 1

As a package substrate, the benefits of glass are substantial. It's extremely flat with lower thermal expansion than organic substrates, which simplifies lithography. And that's just for starters. Warpage, a growing problem for multichip packages, is greatly reduced. Chips can be hybrid bonded to redistribution layer pads on glass. And relative to organic-core substrates, glass provides very... » read more

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