Next Steps For Panel-Level Packaging

Where it’s working, and what challenges remain for even broader adoption.


Tanja Braun, group manager at Fraunhofer Institute for Reliability and Microintegration (IZM), sat down with Semiconductor Engineering to talk about III-V device packaging, chiplets, fan-out and panel-level processing. Fraunhofer IZM recently announced a new phase of its panel-level packaging consortium. What follows are excerpts of that discussion.

SE: IC packaging isn’t new, but years ago it was largely in the background. A given IC package simply encapsulated and protected a chip. Recently, though, packaging has become more important across all industries. What’s different now?

Tanja Braun, group manager at Fraunhofer Institute for Reliability and Microintegration (IZM),Braun: Packaging has gained more importance because it’s enabling applications. It’s driving different technologies. We are now seeing chiplets with active interposers. In fan-out, we have new approaches. We see substrate-based approaches. But we also see a lot of flip-chip on substrate. This is done quite differently than what we’ve seen in the past. We have talked about heterogeneous integration for about 20 years, but at the moment we are doing much more in that direction. It’s not only an ASIC and sensor in one package. There’s a lot of new topics and package configurations. We have double-sided molded antenna integration. We see the integration of shielding layers, passive structures and components, or the combination of different semiconductor compounds in one package. It’s getting much more complex and interesting.

SE: What are the drivers for packaging today and the future?

Braun: We are working on 5G and 6G applications, which are definitely driving this. It’s also important to have cost-effective solutions here. Automotive is now also a bit more open for this. More sensors are moving in automotive. We also see 77GHz radar in fan-out wafer-level packaging technology. Also, you have all these AI applications where you integrate sensors, including edge computing and cloud computing everywhere. That’s also driving a lot of these topics.

SE: One of the challenges for packaging now involves shortages, right?

Braun: Today, the materials are very challenging. To obtain the substrates — especially in Europe, for example — it’s really difficult, and you need high-end substrates for these kinds of applications.

SE: In 2016, Fraunhofer launched the Panel Level Packaging Consortium. This effort was designed to develop panel-level packaging technology. What was that about?

Braun: We saw a lot of interest at that time. We developed a full infrastructure for this technology. There was a lot of new equipment developed four or five years ago, and this is still ongoing. The panel-level consortium offered companies from the equipment and materials industries, as well as OSATs and end users, the opportunity to develop processes and learn about the different process steps along that value chain. We had everything in-house. So you could come and work with us on your materials and equipment along the entire process chain.

SE: Generally, fan-out and other package types are processed using round 200mm or 300mm wafers. What is the motivation behind panel-level packaging? You can process more packages on a panel, right?

Braun: You can reduce the cost when moving from round to larger panels. We did cost modeling here. It also has a positive environmental effect. By going to larger formats and rectangular formats, you can save base material and energy. That has an environmental sustainability impact.

Fig. 1: Fan-out packaging with (a) wafer form and (b) panel form. Source: ASE

Fig. 1: Fan-out packaging with (a) wafer form and (b) panel form. Source: ASE

SE: In the original consortium, what was the panel size you were working with?

Braun: For us, the size was 610mm by 457mm. That is 24 by 18 inches.

SE: Back then, there was an issue with panel-level packaging. Several companies were — and still are — working on panel-level fan-out using different panel sizes. In other words, there are no standards here, right?

Braun: This is a size question, which has not been solved. We’ve seen 600mm by 600mm. One of the favorite formats is also 510mm by 515mm. However, SEMI is still working on standardization in this area.

SE: What were the line and space dimensions of the redistribution layers (RDLs) here? [RDLs are the copper metal connection traces that electrically connect one part of the package to another. They are measured by line and space, which refer to the width and pitch of a metal trace.]

Braun: We went in the direction of 10µm lines and spaces.

SE: For years, several commercial companies have been working on panel-level packaging. Intel has been working on it. ASE and Samsung are working on panel-level fan-out packaging. Where are we in panel-level packaging today? And what are the challenges here?

Braun: There are also other companies that have heavily invested in panel-level fan-out like Powertech and Nepes. There might be some new players looking into that as well. On one hand, you need to make big investments here. You need to install a panel line and you have to fill the line with products. So you need to have applications and very high volumes. Otherwise, you will lose the cost advantage.

SE: It’s safe to say that panel-level fan-out is in production. But it’s not in what many would say mass production among many players. Has it taken longer than you thought to bring it into volume production? Or are we in volume production, but companies are keeping it quiet?

Braun: You don’t see it looking at the final product, so you would never recognize whether the package is manufactured on a wafer or panel. Of course, TSMC is doing fan-out in high volumes, which is on a wafer-level process. Samsung is developing it on a panel. ASE is moving into that. Nepes bought Deca’s facilities in the Philippines. That is potentially a panel process. This technology has reached a mature status. Still, the question that is not fully answered is where are the limits and what are the sweet spots. Does the panel have to follow the same path as a wafer? Could we see it on the high-end? Is it for high-density fan-out? Is there another application? That’s not fully answered.

SE: Recently, Fraunhofer IZM launched the next phase of this consortium. That’s called the Panel Level Packaging Consortium 2.0 (PLC 2.0). Besides Fraunhofer, the consortium includes Ajinomoto, Amkor, ASM Pacific, AT&S, Atotech, BASF, Corning, Dupont, Evatec, Fujifilm, Intel, Meltex, Nagase, RENA, Schmoll Maschinen, Showa Denko Materials, and Semsysco. What is that about?

Braun: The focus is still on that large 610mm by 457mm square panel. That’s 24 x 18 inches. For the Panel Level Packaging Consortium 2.0, we are working on fan-out, which is a molded embedded style. On the same production line with the same size, we also are working on embedded applications for printed circuit boards. This is where we embed active components into printed circuit boards. But for PLC 2.0, what we’re doing at the moment is to look at processes and materials to evaluate current panel-level production limits, especially for fine-line RDLs. So is it possible to go to 2µm lines and spaces? What are the challenges? Is the equipment ready for that? Are the materials ready for that? That’s still not fully answered if the panel can follow the same path as the wafer.

Fig. 2: First results of PLC 2.0: Fully populated panel with embedded chips. Source: Fraunhofer IZM

Fig. 2: First results of PLC 2.0: Fully populated panel with embedded chips. Source: Fraunhofer IZM

SE: What else are you trying to accomplish with PLC 2.0?

Braun: We would like to better understand the limits. What are the current physical limits in panel-level packaging? We’re looking much deeper into warpage and die shift. Die shift is one of the issues that may cause yield problems or may influence the yields, so you have to control that. We also are working on adaptive patterning. For the panel, you need some adaptive structuring. Otherwise, you will not overcome all the tolerance challenges on large-size panels. We plan to go to 2µm lines and spaces. That is the goal. We are even studying going down to 1µm lines and spaces and finding the limits all on a large panel scale.

SE: So for patterning, are you looking at direct write or traditional lithography steppers?

Braun: We have decided to use direct write. We have new equipment here. There is one company in the consortium — Schmoll — that has developed a new laser direct imaging or direct writing tools. They call this direct-write technology MDI. This has been a fruitful cooperation for going into 2µm lines and spaces on a large panel size.

SE: Does adaptive patterning solve the die shift problems?

Braun: Of course, you need measurements and you need fast measurements. That’s the first thing, and you need some tools there. And you need software, and you have to work with a lot of data. It depends on how complex you do the adaptive patterning. Data conversion and bringing that to the machine for each panel requires a lot of work and time. That involves converting and calculating the pattern and the layout.

SE: During the process flow, warpage becomes an issue on a panel. Are the warpage issues different on a panel as compared to a wafer?

Braun: Yes and no. Here’s one statement you can make here — warpage is independent from the different process approaches. If you do RDL first, RDL last, or whatever, warpage is an issue for all of them. The problem is that there are a lot of factors influencing warpage. It makes it very complicated to forecast and simulate. You have to simulate the entire process flow with all of the materials and temperatures. You must perfectly describe the materials. That is a big challenge. The materials change with the temperature over time, as well as with the humidity, and that is a big challenge. First of all, we have to better understand the behavior of the materials. We also have new tools. In the mold tool, for example, you have the chemical shrinkage of the material. You need to see how the material cures. This is more or less the first step of the history of material process. Then, if you have a large panel, there might be temperature differences and material inhomogeneities. Until now, I have not have seen a good thermal mechanical process simulation that can really forecast that. Of course, you can simulate one application. But if you try to transfer to the next one, that might fail.

SE: Is that true for both round wafers and panel?

Braun: It’s for both. Once again, the warpage effects are independent from the shape and the size. For the larger panels, of course, they are heavier. Of course, you have gravity effects. That might even help a bit because it’s much more flat on the table than maybe a wafer. Still, you might have to consider gravity effects. So in R&D, we are trying to better understand the materials. But we are also developing temporary panel handling concepts within the PLC 2.0.

SE: Are the epoxy mold compound (EMC) materials the issue here? Or has warpage been a problem all along?

Braun: It’s been an issue all along. At each process step, the warpage may change. Then, in the next process step, it changes again. In the beginning of the process, you have the mold compound in combination with the silicon. On one side, you start stacking materials layer-by-layer with different thermo-mechanical properties. You add a polyimide with a very high coefficient of thermal expansion (CTE), even if it’s a thin layer. Then you add copper, also with a high CTE. And all of this is influenced by the process temperatures. If you cure the polyimide a bit higher, then maybe the mold will also shrink a bit more. So that is all influencing it.

SE: What’s the end goal for PLC 2.0?

Braun: We would like to further drive the technology. We would like to see the limits of the technology. We would like to better understand the processes. We are seeing a lot of new materials and equipment. We see a big step in equipment and materials. That’s what we need, especially if you go to finer lines and spaces for multiple integration and things like that.

SE: Will we ever see one standard panel size in panel-level packaging? Or will we have several panel sizes for the technology?

Braun: There already are many different sizes introduced in manufacturing. This is due to historical reasons. For example, some have a PCB technology background. Others may have an LCD background with different formats.

SE: Will the lack of standards prevent panel-level fan-out packaging from taking off? Does this make it difficult for equipment makers or not?

Braun: It definitely makes it more difficult for equipment suppliers, as no standard size is obvious. But as different formats are already introduced in manufacturing, I don´t see this as a show stopper. And standardization could perhaps help to further lower the cost for panel-level packaging.

SE: Fraunhofer IZM also recently presented a paper on fan-out packaging for gallium nitride (GaN). What is that about?

Braun: Regarding packaging for gallium nitride, this is for RF applications. That’s different compared to silicon. That is a bit of a challenge here. At the moment, packages for higher frequency with GaN are often very expensive ceramic packages or pre-molded packages. Sometimes, it goes into a QFN package. Of course, this technology is higher frequency, but it’s also higher power. So the thermal dissipation might be very high. That is one of the challenges. Then, a GaN device itself is different to silicon. The pads are usually gold. It’s a gold metallization. The components are very thin. It’s typically between 70µm and 100µm. You have a gold backside metallization, as well. And you might have open vias on the newer components on the backside. You have air bridges on the top side. They allow two traces to cross. They are mechanically sensitive. And so the challenge is to bring that into a cheap plastic package. This is a very interesting application at the moment. We have seen a lot of companies in Europe that are doing GaN or GaAs for the higher frequencies in 5G and 6G applications. They are looking for packaging technologies at higher volumes.

SE: What are the advantages of having RF GaN in a fan-out package?

Braun: First of all, it would be a cheaper package, because it’s a plastic package. And, of course, fan-out has the shortest interconnect packaging wires that you can get at the moment. You have plated vias as the interconnects. No bond wires or flip-chip bumps are involved. The next step is heterogeneous integration. You maybe could have GaN together with silicon or gallium arsenide in one package with short interconnects and no substrate involved anymore. Maybe you can have passive structures or an antenna integrated, as well. And you have a component, which could be easily handled by SMT assembly on the board. That is what fan-out may offer.

SE: We’ve seen fan-out in mmWave, right?

Braun: We already have applications like radar here. That has entered the automotive market with 77GHz. But we have done 94GHz radar systems already, as well. So fan-out has been introduced in the automotive market.

SE: Chiplets are a hot topic, especially if they’re available from a menu that a customer could select from and then integrate into a package. What is your view on chiplets?

Braun: That will happen. For me, it’s more of a question of who will do that in the future. Of course, if I’m the foundry, I can do that. And maybe, if I’m a customer, I can buy everything from one foundry. It could get much more complicated if I want to build my own chiplet. Then, I would need to buy chiplets from different companies and integrate them. So perhaps you could buy that as a product from Intel, TSMC and Samsung. But will the technology become available for smaller companies or end users? Let’s wait and see. There is a lot of standardization needed. It also involves heterogeneous integration. You could do this on an interposer or even on an organic substrate and bring that all together.

SE: For chiplets, there are different die-to-die or die-to-wafer interconnect schemes, such as microbumps and hybrid bonding. Some plan to use existing copper microbumps for the interconnect schemes. Others may use hybrid bonding. How will this play out?

Braun: If you go one step further to hybrid bonding, there might not be many companies that are able to do that in the future. Of course, for miniaturization and integration, it’s a great solution. You could see that for wafer-to-wafer and die-to-die applications. The question is who is able to do that in the end. It’s a good example to see how the backend and front-end are getting much closer. In the end, you need a front-end facility with high-end clean rooms, planarization, and so on to do that, so it’s maybe closer to the front-end than to backend.

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Hugo Pristauz says:

Thanks Mark and Tanja for the good overview. Frankly speaking I’m surprised that evolvement of the technology has progressed less than expected. But I agree with Tanja that panel level packaging can only-pay off when players are in the background who are able to load production lines with huge volumes. Let’s review PLP progress after next three years.

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