tag: RDL

Panel-Level Packaging’s Second Wave Meets Engineering Reality
By Gregory Haley - 16 Apr, 2026 - Comments: 0

Key Takeaways Panel-level packaging is arriving not because the engineering is ready, but because wafer-level economics are breaking down. Glass improves the warpage and dimensional stability problems of organic substrates but introduces a different class of failure modes that require materials solutions, not process adjustments. The central challenges of panel-level processing are m... » read more

The Opportunities And Challenges Of FOPLP Technology
By Teck Lee - 23 Oct, 2025 - Comments: 0

Artificial intelligence (AI) has emerged as a major catalyst for innovation and advancement. The growing demand for AI computing power is driving heterogeneous integration toward larger packaging sizes, sparking increased interest in Fan-out Panel Level Package (FOPLP) technology. This article explores ASE’s practices and developments in this area, delving into the technical intricacies and e... » read more

Glass Substrates Gain Momentum
By Laura Peters - 18 Sep, 2025 - Comments: 1

As a package substrate, the benefits of glass are substantial. It's extremely flat with lower thermal expansion than organic substrates, which simplifies lithography. And that's just for starters. Warpage, a growing problem for multichip packages, is greatly reduced. Chips can be hybrid bonded to redistribution layer pads on glass. And relative to organic-core substrates, glass provides very... » read more

Using Picosecond Ultrasonic Technology For AI Packages: Part 2
By Cheolkyu Kim - 10 Jul, 2025 - Comments: 0

Heterogeneous integration is a key enabler of today’s AI innovations. By bringing together multiple chips with different functionalities, a.k.a., chiplets, AI devices have been able to achieve tremendous performance gains. However, the heterogeneous integration of advanced packages has its own set of process control obstacles that must be addressed, including new interconnect challenges invol... » read more

Physics Limits Interposer Line Lengths
By Bryon Moyer - 19 Jun, 2025 - Comments: 1

Electrical interposers provide a convenient surface for mounting multiple chips within a single package, but even though interposer lines theoretically can be routed anywhere, insertion losses limit their practical length. Lines on interposers — and on silicon interposers in particular — can be exceedingly narrow. Having a small cross-section makes such lines resistive, degrading signals... » read more

Front-End Technologies Are The New Back-End Tools: Using Picosecond Ultrasonics Technology For AI Packages, Part 1
By Cheolkyu Kim - 10 Jun, 2025 - Comments: 0

If you are a part of the semiconductor industry or simply someone interested in the field, you have likely heard what has become a common refrain: the back-end of the process is becoming more like the front-end of the process. In other words, the technologies that were once exclusively deployed in the first part of the process are being used to meet the increasingly stringent requirements of ad... » read more

Fine-Line RDL Structure Analysis of Fan-Out Chip-on-Substrate Platform
By ASE - 17 Apr, 2025 - Comments: 0

Abstract: "The demand for high bandwidth memory (HBM) has driven the need for advanced packaging solutions, particularly those involving fan-out layers to interconnect wafers within packages. To meet the high-bandwidth requirements of the Fan-Out Chip-on-Substrate (FOCoS) technology platform, additional layers are required. However, as the number of fanout layers increases, significant chall... » read more

Big Changes Ahead For Interposers And Substrates
By Gregory Haley - 24 Mar, 2025 - Comments: 1

Interposers and substrates are undergoing a profound transformation from intermediaries to engineered platforms responsible for power distribution, thermal management, high-density interconnects, and signal integrity in the most advanced computing systems. This shift is being driven by AI, high-performance computing (HPC), and next-generation communications, where the need for heterogeneous ... » read more

Advanced Packaging Evolution: Chiplet And Silicon Photonics-CPO
By Vincent Lin - 20 Feb, 2025 - Comments: 0

As we enter the AI era, the demand for enhanced connectivity in cloud services and AI computing continues to surge. With Moore’s Law slowing down, the increasing data rate requirements are surpassing the advancements of any single semiconductor technology. This shift underscores the importance of heterogeneous integration (HI) as a crucial solution for alleviating bandwidth bottlenecks. Tod... » read more

Innovations Driving The Advanced Packaging Roadmap: Part One
By Keith Best - 14 Jan, 2025 - Comments: 1

Advanced IC substrates (AICS) have been marching toward the 2µm line/space (L/S) redistribution layer (RDL) technology node for some time (figure 1). However, many questions remain about the ability of organic substrates to meet the line/space requirements of the next generation of advanced packages (AP), those below 2µm L/S and perhaps to 1.5µm L/S. Simply put: are organic substrates up to ... » read more

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