New Insights Into IC Process Defectivity

Finding critical defects in manufacturing is becoming more difficult due to tighter design margins, new processes, and shorter process windows.

Process marginality and parametric outliers used to be problematic at each new node, but now they are persistent problems at several nodes and in advanced packaging, where there may be a mix of different technologies. In addition, there are more processes at each node, more customization at the behest of large chipmakers, and more differentiation from one foundry to the next even at the same node. As a result, one solution no longer solves all problems.

To compound these issues, a variety of other new processes, such as hybrid bonding, create both random and systematic defects early in the manufacturing and assembly flows, when new defect mechanisms are not fully understood.

To address these issues, engineers rely on an array of inspection methods, smart defect classification, and machine learning analytics to weed out killer defects during earliest stages of product ramps. But even then, there are so many options and customizations in designs that what works in one instance doesn’t necessarily work in another. In fact, what works in one design may not work in a derivative of that same design.

Yield improvements, which used to begin after GDSII code was delivered to the fab, now must begin at the design stage. And they must be accounted for early in the design flow, when fixing a potential problem is less expensive and more effective.

“Chipmakers are focused on ramping to yield entitlement in high-volume manufacturing sooner with faster process ramps,” said Vivek Jain, product management specialist at Synopsys, noting that fabs no longer segment process tool operations from defect inspection and testing results. “Bringing equipment, defectivity, and test results together does improve the depth of understanding to potentially speed root cause analysis of failures.”

Another big change is an increased use of ML models, which can help pinpoint the cause and frequency of drift in equipment and processes. “We’re using modeling to predict failures that come from the malfunction of a piece of equipment, which can account for up to 50% of all failures,” said David Meyer, CEO and co-founder of Lynceus. “We analyze the data from FDC (fault detection and classification) and environmental conditions inside the chamber, and that ties into the next inspection step. By predicting the results, there are steps we can take to reduce inspection time by only sampling units that don’t pass ML predictions.”

Meyer added that initial ROI wins become the selling point for the next level of process control, which can involve feed-forward and feed-back analyses. “The market is really young, but anyone manufacturing automotive chips is facing increasing quality requirements. They want to know what we can do to improve quality without impacting capacity.”

There is still more work to be done, particularly in the area of linking data from tools, manufacturing execution systems, and metrology to existing IT infrastructure. Today, this remains a bottleneck. But it’s a problem that will need to be solved, because defect inspection, localization, and classification lie at the heart of semiconductor yield improvement programs.

In general, as features shrink, so do defects of interest. Defect inspection and review continue to play critical roles in pinpointing process excursions during device manufacturing, but they are being stretched. This is why yield management systems are becoming even more critical for identifying the origin of problems. Potential issues need to be addressed early enough to avoid costly rework steps, or worse, failures in the field.

Not all defects cause failures, though. The challenge is identifying the killer or latent defects found in the device’s active area, while weeding out nuisance defects in field areas that do no harm. No device is perfect, even at mature nodes. But advanced nodes have more problems. Variability becomes more troublesome in new processes, where thin metal interconnects can become so thin that they lose connection (electrical opens). In addition, misaligned features may connect when they shouldn’t connect, causing shorts. Marginal defects must be closely analyzed to ensure the most robust process.

Machine learning and analytics also can identify better and worse tool combinations, arriving at routing options that can improve yield. “In fabs, people tend to know when specific tools, like lithography and etch, work well together,” said Dieter Rathei, CEO of DR Yield. “But this is empirical information, so we developed an algorithm that can capture these relationships. This is computationally intense and runs about an hour, but when it’s done you know your good tool combinations and problem tool combinations and can route wafers through to deliver higher yield.”

Tools of the trade get better
Yield engineers typically rely on a combination of optical inspection and e-beam inspection tools. But they are adding new tools into the mix, as well. For example, X-ray inspection, which identifies imperfections in solder bumps, is becoming more popular in assembly operations. And recently, failure analysis tools have begun playing a more active role in root-cause analysis due to faster turnaround time, which in turn results in faster yield learning.

Nevertheless, optical systems remain the workhorses, providing inputs to in-line statistical process control and process monitoring. The key for defect inspection is signal-to-noise ratio (SNR) and contrast, not resolution. “These inspection tools are often connected to the factory host through which process engineers review spec charts and Cpk data to identify trends that might indicate abnormal deviations,” explained Burham Ali, inspection product marketing manager at Onto Innovation. “Additionally, the deployment of advanced process control techniques — to continuously feed data forward or back from the inspection to process tools — allows for the ability to make micro adjustments every time the data falls out of control limits, and helps improve Cpk in real-time without outside intervention. This also reduces the amount of rework required, which results in cost savings.”

Companies offering defect inspection systems include KLA, Onto Innovation, Applied Materials, Hitachi High-Tech, JEOL and ASML. Those systems are either amplitude-based or intensity-based, employing brightfield illumination, darkfield illumination, or a combination of both. Brightfield inspection is best at detecting flat defects or in-trench defects between structures, while darkfield excels at detecting scattering defects on top of structures. SEM suppliers include KLA, Applied Materials and ASML, with ASML offering a multi-beam e-beam inspection system for achieving higher throughput than single-beam systems. Defects on wafer maps are detected by comparing die-to-die images, so the subtracted information fills in the defect wafer map. Die-to-database comparisons also are used.

Machine learning is beginning to infiltrate these processes. Defect classification is one area where ML algorithms already provide faster and more accurate classification of defects over manual characterization by humans. “ML- and AI-based tools are used to identify unique patterns on the wafer, even in the presence of other defects on the wafer,” said Onto’s Ali. “And they can classify patterns into bins based on an extracted signature. The patterns can include systematic defects like a CMP scratch or chuck markings. This proactive approach not only improve inline monitoring, but also provide better lot and wafer disposition strategies.”

Getting electrical results
In general, electrical results are not widely available until wafer probe (ATE), when each device is electrically tested for functional defects by applying specific test patterns.

“We get a lot of requests to add particular features to our ‘quality module,’ as we call it,” said DR Yield’s Rathei.”And it’s a very sophisticated tool, with a lot of configuration options with classic algorithms, and then some algorithms that we have improved on. For instance, the classic AEC (Automotive Electronics Council) algorithms require normal distributed data. Electrical test data are rarely Gaussian-distributed. That’s why we also made variants that do not require a Gaussian distribution for the test data, and other robust variants in the software.”

Even before wafer probe, there are some opportunities to examine defects after transistors have been contacted to the first levels of interconnect. For instance, PDF Solutions provides a custom e-beam prober that can detect electrically relevant defects at the middle-of-line. The DFI system uses test vehicles (IP cells) inserted in the device with contact pads. That allows an e-beam system to read the electrical responses from the characterization cells to detect failures, including marginal failures due to systematic defects.

ML and analytics
Machine learning is just beginning to influence fab operations on a large scale. The challenge is that most analyses are not “one and done.” And algorithms, no matter how efficient, still require modification, especially when it suits the particular needs of semiconductor operations.

Outlier detection algorithms have been in use for some time to flag devices performing differently than other chips on the same wafer based on a single parametric test (univariate) or two (bivariate) or more tests simultaneously. Companies use part average testing (PAT) that works on statistical control limits during manufacturing to catch potential long-term reliability failures. They were first developed for high reliability markets including automotive, medical, and aerospace. The most common are Z-PAT (z-axis PAT), cluster analysis and good die bad neighborhood (GDBN) that surround failing die.

Depending on the device’s quality requirements, bivariate and trivariate testing is performed. Bivariate refers to correlating two tests simultaneously, while multivariate refers to three or more tests being cross-correlated simultaneously. The downside to these methods is the computing resources needed to run them.

Inspection during assembly and packaging
Though the defects engineers are concerned with during assembly and packaging are generally larger than in front-end processes, there is still a need to detect critical defects in solder bumps, underfill, and packaged devices (such as cracks and voids). The same is true for laminate substrates within substrates, which today can be very large with advanced packaging where chiplets are being integrated. Defect detection tools for back-end processes are offered by Onto Innovation, Bruker, Nordson Test & Inspection, and others.

One of the challenges for optical inspection and X-ray inspection methods is adequate defect detection over large surfaces that often exhibit warpage and tilt. Warpage causes slight differences in co-planarity between chip and substrate, causing some micro-bumps to insufficiently connect with pads below, a failure called non-wet.

“Consider an advanced processor that’s 50 to 60mm, as an example,” said Frank Chen, director of applications and product management at Bruker. “Because of its large size, it’s challenging to process without any warpage. Nevertheless, if the die-attach tool is tuned to the center of its process window, it can pass inspection and be manufactured with high yields. The issue is that the tolerance can be very narrow. As soon as you have a bit of die tilt on top of the warpage, you have non-wet issues.” X-ray metrology can provide high contrast when it comes to metals, including solder bumps and microbumps (see figure 1).

Fig. 1: Large packages require fine control on die-tilt to avoid non-wet issues due to its high warpage. Source: Bruker

“X-ray is useful for identifying process excursions because it can be inserted earlier in the line,” said Chen. “It’s essentially a technique that you can insert right after you attach the dies, even before reflow and molding. You can really capture what’s happening on the wafer with respect to die placement accuracy and tilt, and these variations all relate to the bond quality.”

As with front-end inspections, these techniques do a good job of catching outright failures. The problem is they don’t catch all the marginal defects, which can find their way into the field.

“As SPC reporting gets more sophisticated and you’re looking at tighter control limits that are inside of spec limits, then you’re able to start identifying process drift, and that’s where the real value of the tools is coming in today,” said Brad Perkins, product line director at Nordson Test & Inspection. “It’s not letting escapes get out to the field, which is of course monumentally important when you look at devices used in autonomous driving.”

Perkins sees a trend toward 100% inspection using the company’s MRS tool, but with the caveat that it does not lead to a bottleneck in operations.

Conclusion
Process marginality and parametric outliers are now persistent problems at most technology nodes. Engineers are finding a combination of inspection techniques, along with integration of design, inspection, and testing areas helps identify random and systematic defects early in the process flow. But advanced packaging will require greater investment in inspection and analysis to cope with the multiple challenges of integrating more and more devices on a substrate and in a package. And across all of these process steps, machine learning and AI algorithms are poised to play an increasingly larger role in fab, assembly, and testing operations to ensure final device quality.

Related Reading
Journey From Cell-Aware To Device-Aware Testing Begins
Better test quality is required as devices become more heterogeneous and denser and use cases become more critical; tradeoffs are cost and time.
Streamlining Failure Analysis Of Chips
Identifying nm-sized defects in a substrate, mixing FA with metrology, and the role of ML in production.